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SCSI Overlap Command Check Circuit

IP.com Disclosure Number: IPCOM000104715D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Ishibashi, K: AUTHOR [+3]

Abstract

Disclosed is a SCSI overlap command check circuit for a SCSI-2 target device. When a hardware protocol sequencer handles the SCSI protocol instead of a microprocessor (MPU), this overlap command check circuit checks whether a second command is issued before a first command is processed. If an overlap command condition is detected, then this circuit tells MPU that the second command is queued by the second initiator.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 69% of the total text.

SCSI Overlap Command Check Circuit

      Disclosed is a SCSI overlap command check circuit for a SCSI-2
target device.  When a hardware protocol sequencer handles the SCSI
protocol instead of a microprocessor (MPU), this overlap command
check circuit checks whether a second command is issued before a
first command is processed.  If an overlap command condition is
detected, then this circuit tells MPU that the second command is
queued by the second initiator.

      Fig. 1 shows this circuit.  D-type flipflop (D-F/F) 1
represents an eight bit register.  Current Initiator ID is stored at
the beginning of SCSI Selection Phase by the signal of CURRENT
INITIATOR ID WRITE.  D-F/F 2 also repre sents an eight bit register.
When a command is in process and MPU wants to know if another
initiator accesses or not, then MPU writes any queued initiator ID in
this register by a write signal Q-ID WT.  When registers 1 and 2 have
the same active ID bit, the output of comparater 3 becomes to be an
active state and D-F/F 4 latches this state at the end of SCSI
Selection Phase.  The output of D-F/F 4 interrupts MPU to tell that
the same ID as the ID set by MPU was detected at SCSI Selection.

      Fig. 2 is the timing chart.  Assume Q-ID output is 'F0h' which
means Initiator ID's 7, 6, 5, 4 are queued.

1.  LSCSI bus phase changes from Arbitration to Selec tion.  SCSI
    -SEL signal goes low.

2.  According to -SEL being low, CURRENT INITIATOR ID WRITE signal
    l...