Browse Prior Art Database

Chip-Set For Massively Parellel Simple Instruction Multiple data Computers

IP.com Disclosure Number: IPCOM000104795D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Buranits, G: AUTHOR [+3]

Abstract

New architecture building-blocks are disclosed for processors, random access memories, and communication facilities in massively parallel computers. New layouts are shown for interconnection networks allowing the modular design of Single Instruction Multiple Data (SIMD) [1,2,3,4] parallel machines. The main inventions presented in this document are as follows.

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Chip-Set For Massively Parellel Simple Instruction Multiple data Computers

      New architecture building-blocks are disclosed for processors,
random access memories, and communication facilities in massively
parallel computers.  New layouts are shown for interconnection
networks allowing the modular design of Single Instruction Multiple
Data (SIMD) [1,2,3,4] parallel machines.  The main inventions
presented in this document are as follows.

      Communication and memory facilities are provided for a wide
range of massively parallel machines.  These two resources, i.e.,
communication and memory, are integrated on the same chip, dubbed
Memory and Communication Server (MACS).  The MACS chip can be
reconfigured to support massively parallel architecture designs with
a varying number of processors and topologies for interconnection
networks.  A MACS chip has a number of server nodes.  Each node
consists of some random-access memory (RAM) and communication
facilities.  The communication facilities of all nodes are linked,
forming a structure that allows its modular growth by connecting MACS
chips together.  Data pins to access a RAM node are also used to
access the communication facilities of the same node.  This mechanism
is convenient for SIMD machines since processing elements (PEs) never
access memory and communication resources simultaneously.  Present
technology capabilities suggest that a MACS chip can host 16 server
nodes, each having 32K bytes of RAM.  Integrating memory and
communication on the same chip reduces pin requirements of the whole
architectural design and also offers a reduction of real-estate at
the board and back-plane levels.

      Processing facilities are provided by the processing element
array server (PEAS) chip.  This chip integrates a number of 8-bit
processors, small local RAM, and connections to configure parallel
machines with an arbitrary number of (PEs).  The main novelties in
the PEAS chip are its Conditional Unit and the ability of each
processor to address its own internal RAM independently.  This RAM
plays a key role as a queueing resource in the implementation of
parallel routing algorithms in SIMD machines [4].

      The...