Browse Prior Art Database

Selecting Predecoded Instructions with a Surrogate

IP.com Disclosure Number: IPCOM000104800D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 138K

Publishing Venue

IBM

Related People

Jones, GD: AUTHOR [+2]

Abstract

Presented is an idea for allowing more, very-complex, compound instructions to be added to the instruction sets of current and future signal processors. The particular technique described requires the use of on-chip storage (RAM and/or ROm) to hold predecoded (no\ decode action required) instruction information that can be accessed during the instruction decode phase, and substituted for the instruction in IDR at that time. The method described is general in nature and could also be used in other types of microprocessor engines. It is an especially promising way to extend the instruction sets of current signal processor architectures.

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Selecting Predecoded Instructions with a Surrogate

      Presented is an idea for allowing more, very-complex, compound
instructions to be added to the instruction sets of current and
future signal processors.  The particular technique described
requires the use of on-chip storage (RAM and/or ROm) to hold
predecoded (no\ decode action required) instruction information that
can be accessed during the instruction decode phase, and substituted
for the instruction in IDR at that time.  The method described is
general in nature and could also be used in other types of
microprocessor engines.  It is an especially promising way to extend
the instruction sets of current signal processor architectures.

      One way to implement extended compound instructions involves
having on-chip memory to hold very long, predecoded instruction
words.  Predecoded instructions are individual instructions
represented directly in machine executable form (no decode required);
they are composed outside the processor and loaded into internal
storage via an existing interface path or may be held in ROM.

      In order to select a predecoded instruction, it is proposed
that each such instruction be represented in programs by a surrogate,
a conventional (simplex) instructions used to represent it.  Such
surrogate instructions are always of the simplex variety (not
compound), and will always contain an address designating which
precoded instruction it represents.  When the simplex surrogate is
recognized during the instruction decode phase, the decode controls
will call the predecoded instruction to be placed in the execute
register in its place.

      Suppose some specific storage is provided within the processor
to hold very long pre-decoded instructions.  The instructions which
could most beneficially be held in this form are the compound
instructions which are composed off-chip and loaded in the on-chip
memory some time prior to their use.  Further, suppose that space is
provided on-chip for such composed instructions.

      Now, to call a predecoded instruction for execution, it is
necessary to have a conventional (simplex) instruction- a surrogate -
with a selection field specifying which composed instruction to load
into the execute register.  This surrogate instruction may also
contain an operand field that will be used to resolve an effective
address or operand which will be used when the instruction executes.

      A picture of a possible logic flow is shown in Fig. 1.

      Fig.1 represents a fragment of the instruction pipeline path.
This flow is similar to previous practice, except that when a
particular type of instruction (a surrogate) appears in the IDR, a
select field within the instruction is used as an address for PDIM.
Then, the particular word accessed from PDIM is a predecoded compound
instruction which is emitted to the MUX.  In the meantime, the fact
that a surrogate instruction is in the IDR is recognized...