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Design of Scan-Based Delay Testable Circuits

IP.com Disclosure Number: IPCOM000104815D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 155K

Publishing Venue

IBM

Related People

Kundu, S: AUTHOR [+2]

Abstract

There are various models for AC or delay testing, such as the transition fault model [1], small (gate) delay fault model [2], and path delay fault model [3]. The path delay fault model is the most rigorous and stringent one, since full testability under this model implies full testability under any other delay fault model.

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Design of Scan-Based Delay Testable Circuits

      There are various models for AC or delay testing, such as the
transition fault model [1], small (gate) delay fault model [2], and
path delay fault model [3].  The path delay fault model is the most
rigorous and stringent one, since full testability under this model
implies full testability under any other delay fault model.

      Irrespective of the model chosen, the minimum requirement for
AC testing is a two-pattern test.  There are two established
techniques for applying two patterns in a sequence:  one is through
scan and the other is to cycle a system once using a system clock.
However, since we do not have independently controllable latch
outputs, applying any two arbitrary patterns in a sequence by the
established methods is impossible without extra hardware (holding
latches) with unacceptable cost overheads.  Thus, this restricts the
number of feasible two-pattern tests that can be applied, which in
turn limits the number of delay faults that can be tested, resulting
in a large number of untestable AC faults.  Disclosed is a design
technique that results in 100% AC testable circuits under the path
delay fault model.  This also ensures that the circuits are 100% AC
testable under any other delay fault model, as well as fully testable
under the single stuck-at fault model, and in case of CMOS
implementation, fully testable under the transistor stuck-open and
stuck-on fault models.

      Consider the Hoffman model of a sequential circuit as shown in
Fig. 1.  The proposed design methodology consists of:

o   a modification of the combination portion of the circuit to make
    it fully testable;
o   a minor modification of the scan chain to provide a global-set
    and global-reset line for the L2 latches.

      The slight modification required by (b) above is easily
accomplished, as shown in Fig. 2.

      The output of the L2 latches represent a state of a finite
state machine.  Each latch represents a state variable.  The outputs
of the combinational circuit can be classified as internal (inputs to
L1 latches) and external (primary outputs).  The proposed design
methodology is as follows:

1.  By using additional (state) variables, the original states are
    encoded into a unidirectional error-detecting code.  The
    combinational circuit also changes correspondingly.  For
    definitions and procedures, please refer to [4].  All the output
    functions now have the property that they are unate in the state
    variables.
2.  A partial irredundant binary decision diagram (BDD) for the new
    combinational logic is constructed, by selecting primary inputs
    as decision points.  The left nodes of this construction must be
    unate functions of state variables.
3.  The above partial BDD is realized as a circuit by using a MUX or
    NAND-NAND or NOR-NOR logic for the decision points, and any
    irredunda...