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Condition Code Setting in a Pipelined Processor during Parallel Execution of Inherently Sequential Instructions

IP.com Disclosure Number: IPCOM000104817D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Gregoire, DG: AUTHOR [+2]

Abstract

Pipelined processors which permit two independent fixed point independent fixed point operations to execute in parallel may be utilized to "collapse" two dependent addition/subtraction operations into one single-cycle operation via a three-input adder. These techniques correctly generate all sums and condition code settings as though the two additions were executed serially; however, a problem is generated in the event of a carry (CA) and overflow (OV). The "atomic" nature of the second edition is lost when utilizing a three-input adder to generate correct CA and OV flags, although the sum and other condition codes are preserved.

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Condition Code Setting in a Pipelined Processor during Parallel Execution of Inherently Sequential Instructions

      Pipelined processors which permit two independent fixed point
independent fixed point operations to execute in parallel may be
utilized to "collapse" two dependent addition/subtraction operations
into one single-cycle operation via a three-input adder.  These
techniques correctly generate all sums and condition code settings as
though the two additions were executed serially; however, a problem
is generated in the event of a carry (CA) and overflow (OV).  The
"atomic" nature of the second edition is lost when utilizing a
three-input adder to generate correct CA and OV flags, although the
sum and other condition codes are preserved.

      The following equations may be utilized to derive the correct
CA and OV settings for the second add operation utilizing only two
carry bits from Execution Unit A and four carry bits from Execution
Unit B, as depicted in the accompanying figure.

CA =  (       cObl &  cObs)  |
      (^cOa &  cObl & ^cObs) |
      (^cOa & ^cObl & cObs);

OV =  (       ^cla & ^cObl & ^cObs &  clbl & ^clbs) |
      (       ^cla & ^cObl & ^cObs & ^clbl &  clbs) |
      (^Coa &        ^cObl &  cObs & ^clbl & ^clbs) |
      (^cOa &  cla &  cObl & ^cObs &  clbl & ^clbs) |
      (^cOa &  cla &  cObl & ^cObs & ^clbl &  clbs) |
      ( cOa &         cObl & ^cObs...