Browse Prior Art Database

Dense High Performance Memory Package

IP.com Disclosure Number: IPCOM000104825D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Gillett, JB: AUTHOR [+4]

Abstract

Irvine Sensors has developed a process for stacking integrated circuit chips to form a dense cubic package. The chips are bonded into a block, the lower surface ground flat, and connections are deposited on the lower surface. The technique has two constraints: (1) heat dissipation is limited by the thermal conductivity of silicon; and (2) a faulty chip in the block requires that all the chips be discarded, since it is not reworkable. This article addresses both of these limitations.

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Dense High Performance Memory Package

      Irvine Sensors has developed a process for stacking integrated
circuit chips to form a dense cubic package.  The chips are bonded
into a block, the lower surface ground flat, and connections are
deposited on the lower surface.  The technique has two constraints:
(1)  heat dissipation is limited by the thermal conductivity of
silicon; and (2) a faulty chip in the block requires that all the
chips be discarded, since it is not reworkable.  This article
addresses both of these limitations.

      In this disclosure, each chip is treated independently.
Optionally, decoupling capacitors are attached to the chip as in Fig.
1.  They will be shown in subsequent figures, but may be omitted to
increase chip-packing density.

      A heat sink of suitable material (good thermal conductivity,
Coefficient of Thermal Expansion close to that of silicon) is bonded
to the chip and the structure made into a block with an encapsulant
(Fig.  2).  This provides a surface on which to make the chip
connections (Fig.  3).  At this stage the chip can be individually
tested and burned in.

      Good chips are then stacked into a block, aligned and clamped.
A conceptual sketch of a clamp is seen in Fig. 4, but other designs
are practical.

      Fig. 5 shows an example of the application of the blocks in a
memory sub-system, in which the control logic chips and the memory
blocks share the same cooling technology.

      Exa...