Browse Prior Art Database

Single-Ended Output Control for Differential Clock Generator Circuit

IP.com Disclosure Number: IPCOM000104847D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 92K

Publishing Venue

IBM

Related People

Strom, JD: AUTHOR

Abstract

Clock generator circuits that drive logic appropriately at functional cycle times may cause portions of logic to be untestable at low cycle times or during DC testing. This occurs because at low cycle times or at DC the reference output and delayed output of a Clock Generator circuit which generates two low-level differential signals, which are ninety degrees out of phase in functional mode, can have the same value. These low-level outputs are converted to CMOS level outputs by a circuit such as the one shown in Fig. 1. It can also occur when an output and an inverted output, which may come from the same differential pair, are used to drive logic.

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Single-Ended Output Control for Differential Clock Generator Circuit

      Clock generator circuits that drive logic appropriately at
functional cycle times may cause portions of logic to be untestable
at low cycle times or during DC testing.  This occurs because at low
cycle times or at DC the reference output and delayed output of a
Clock Generator circuit which generates two low-level differential
signals, which are ninety degrees out of phase in functional mode,
can have the same value.  These low-level outputs are converted to
CMOS level outputs by a circuit such as the one shown in Fig. 1.  It
can also occur when an output and an inverted output, which may come
from the same differential pair, are used to drive logic.

      The following circuit provides independent control of the
reference and delayed outputs as well as the independent control of
differential outputs which would normally be the logical opposite of
each other.

      The output 24 of the disable circuit shown in Fig. 3 is
connected to node NET14 in the pre-drive circuits shown in Fig. 1.
The input to the disable circuit is labeled as A5 in the disable
circuit schematic in Fig. 3.  When the input goes low, device T10
turns on while T0 turns off, pulling the base of NPN Q4 to VDD or 3.6
volts.  The emitter of NPN Q4 goes to 2.8 volts which turns off NPN's
Q7 and Q14 in the pre-drive circuit in Fig. 1 since their bases are
at 1.6 volts.  Since NPN's Q7 and Q14 are off, nodes NET5 and NET6 go
high to 3.6 volts and outputs 20 and 21 go high to 2.8 volts in Fig.
1, which corresponds to a logic "1".

      When the input of the CMOS - current test circuit in Fig. 2 is
high, the base of NPN Q18 is pulled low by device T0 and NPN's Q18,
Q12 and Q8 conduct no current.  When t...