Browse Prior Art Database

Redundant System Bus

IP.com Disclosure Number: IPCOM000104859D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Holm, I: AUTHOR [+3]

Abstract

For data/address buses of increasing width no additional wiring is required for changing from the conventional parity check to an error detection/correction (EDC) mode. This applies to bus widths of up to 8 bytes. For multiprocessor applications or parallel processor systems the availability of EDC offers considerable advantages, as one or several bits that have failed on the system bus can be corrected without a system stop.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 78% of the total text.

Redundant System Bus

      For data/address buses of increasing width no additional wiring
is required for changing from the conventional parity check to an
error detection/correction (EDC) mode.  This applies to bus widths of
up to 8 bytes.  For multiprocessor applications or parallel processor
systems the availability of EDC offers considerable advantages, as
one or several bits that have failed on the system bus can be
corrected without a system stop.

      The advantages are fewer failures, error correction, and an
exchange of system components before complete failure.

      The invention is realized by a programmable interface.  By
using a jumper or shift chain initialization, it is possible to
choose between the state-of-the-art parity check or EDC.  This
permits using different interfaces during the transition period.

      To avoid performance losses, it is proposed to use an EDC
feature with a bypass (see figure).  For this purpose it is assumed
that for most of the time there are no errors, which means that any
data items received may be processed immediately.  The EDC feature is
used in parallel.  If no error is detected, processing proceeds
without any delay.  If bits have to be corrected as a result of an
error, which may be indicated, processing is stopped and subsequently
restarted with corrected data.  Thus, there is only a performance
loss but no system stop in such cases.

      Hard errors on the system bus (failure of plug...