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Interrupt Mechanism for Optimizing Data and Control Data Transfers

IP.com Disclosure Number: IPCOM000104869D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Clark, A: AUTHOR [+2]

Abstract

Early low-end S/370 machines (Micro Channel*/370) had a deficiency in I/O data transfers such that a large transfer could block a smaller transfer which contained control information. The problem has previously been handled by not allowing large single data transfers to occur, resulting in increased programming overhead and lower system performance due to the need to segment transfers with code. This mechanism specifies a solution to this problem by providing hardware to interrupt large transfers for the purpose of allowing smaller control transfers to occur.

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Interrupt Mechanism for Optimizing Data and Control Data Transfers

      Early low-end S/370 machines (Micro Channel*/370) had a
deficiency in I/O data transfers such that a large transfer  could
block a smaller transfer which contained control information.  The
problem has previously been handled by not allowing large single data
transfers to occur, resulting in increased programming overhead and
lower system performance due to the need to segment transfers with
code.  This mechanism specifies a solution to this problem by
providing hardware to interrupt large transfers for the purpose of
allowing smaller control transfers to occur.

      The affected application in low-end system S/370s such as the
Micro Channel/370 uses a Micro Channel platform to satisfy the I/O
requirements.  In this environment, a bus-to-bus adapter and custom
microcode which resides in the Micro Channel domain emulates the
traditional S/370 channel.

      Previous adapters provided only a path for bulk transfers to
the Micro Channel for processing.  Small control transfers had to
share the same path requiring any transfer in progress to terminate
before the control transfer could initiate.  More recent
implementations have used an on-card microprocessor to assist in
S/390 channel and control unit emulation.  The presence of the
microprocessor on the adapter card has made possible an alternate
path for S/390 data where portions can be transferred to adapter
storage for control purposes.

      The alternate path includes a special port built into the
interface hardware which can be programmed separately from the
controls for bulk transfers.  When the on-card microprocessor has
completed specifying the transfer parameters such as address, address
checking, byte count, etc., the hardware will continue the bulk
transfer unt...