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Dealer Instruction Processing Unit Governor - Determining the Segment Switch Depth

IP.com Disclosure Number: IPCOM000104870D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 104K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+3]

Abstract

This article describes a DIG processor organization that can be organized around the concept of three units:

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Dealer Instruction Processing Unit Governor - Determining the Segment Switch Depth

      This article describes a DIG  processor  organization that can
be organized around the concept of three units:

o   DEALER        - ISSUES TAGGED INSTRUCTIONS
o   IPU         - EXECUTES INSTRUCTIONS
o   GOVERNOR - MAINTAINS THE ONLY RECOVERABLE MACHINE STATE
that play  specific  roles  in  the  overall  processing  of
instructions.    What makes DIG organizations different from
processor organizations in general is that the  GOVERNOR  is the sole
means of generating a recoverable machine state.

      The  two  central  organizational points within a DIG design
are:   TAGGING OF INSTRUCTIONS and  HANDLING  OF  BRANCHES.  DIG
achieves  parallel  execution  of  instructions  in the original
program by using the TAGS that are generated during the first-pass
processing  of  instructions.    Instructions that  have different
TAGS can be executed in parallel unless they have receiving
obligations that make  this  impossible.  The  instruction
interdependencies derived during the first pass  specify  a  portion
of  the  eventual  TAGS, and  the remainder  of  the  TAG is
generated by the context in which the  instruction  is  used.    The
sending   and  receiving obligations  for  instructions  given
different TAGS are also created  during  this  first  pass.     The
DEALER   issues instructions  that have been TAGGED.  The purpose of
the TAG is to identify implicit instruction interrelationships  that
relate   to   a  register  file  associated  with  the  TAG.
Instructions with the same TAG can only be done in  parallel if  the
conceptually  earlier  instruction  does  not set a register  that
the  other  instruction  needs  for   input.  Instructions  with
different TAGS are not related except by specific  indicators  that
convey  sending  and   receiving obligations.

      The   handling   of   BRANCHES   is  a  central  motif  that
interrelates  the  three  functional  units.  It  is  at   a
branch-like  point  that  instructions  that  have  new TAGS appear
or the continuation  of  instructions  with  existing TAGS  are
permitted.  The processing of Branch Wrong Guesses (BWGs) helps
reorganize  the  instructions   and   Z-SEGMENT SWITCHES (ZSSs) and
provides   for  reentry  into  the previously processed instruction.
This entry creates new  TAGS  as  the Segment  Switch  index  and
Path index are also part of the TAGS.  A  single  instruction that
appears multiple times in the execution sequence will appear with
different  TAGS  and may be executed in parallel with itself.

      DIG designs are based on developing a parallel representation
of an execution sequence   with   the characteristics  that  create a
considerable homology to the original I-TEXT in...