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Browse Prior Art Database

Memory Array Integrated Multiple Input Signature Register

IP.com Disclosure Number: IPCOM000104888D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 104K

Publishing Venue

IBM

Related People

Sager, GS: AUTHOR [+2]

Abstract

The subject of this disclosure is a design which incorporates the Signature Register or Multiple Input Signature Register [*] into the data output register of the memory array, minimizing the number of logic circuits to implement the Multiple Input Signature Register and permitting circuit, power and chip area reductions for a given Array Built-in Self-Test specification.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Memory Array Integrated Multiple Input Signature Register

      The subject of this disclosure is a design which incorporates
the Signature Register or Multiple Input Signature Register [*] into
the data output register of the memory array, minimizing the number
of logic circuits to implement the Multiple Input Signature Register
and permitting circuit, power and chip area reductions for a given
Array Built-in Self-Test specification.

      High performance array macros designed for inclusion into logic
chips usually have address and data input registers plus array data
output registers.  To minimize the delay through these registers,
they do not follow double-latch design.  Instead, the functional
signal paths to and from the array are bounded by single-latch
registers, for array input latches and array output latches.  The
array output goes directly to a latch point and on to the logic
function.  In our example (see figure) the array data output bits are
L2* latches on ARRAY_CLOCK_2 (there is still an L1 latch paired with
each L2* latch; it is used for scan purposes and as the master stage
for the Multiple Input Signature Register, the array data does not
pass through it).  This method also adds an L4 latch to form the
slave stage of the Multiple Input Signature Register.  The L2* is not
part of the Multiple Input Signature Register but supplies data to
the Multiple Input Signature Register, which operates through the L1
and L4, as shown in the figure.

      Note that in practice, specific bits of the Multiple Input
Signature Register are tapped off and exclusive ORed with the
feedback to its first bit to make it behave (if it were functioning
autonomously) as a maximal length Linear Feedback Shift Resister.
Evidence exists that choosing its characteristic polynomial as a
primitive polynomial reduces aliasing.

      A description of the operation is as follows: Refere to the
figure, a 3-bit Multiple Input Signature Register.  The use of three
bits is to simplify the explanation of Multiple Input Signature
Register operation, although it would have many more bits in actual
practice.  The initialization of the Multipl...