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Improving the Bandwidth of a Single Cache Directory and Array

IP.com Disclosure Number: IPCOM000104893D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 151K

Publishing Venue

IBM

Related People

Emma, P: AUTHOR [+5]

Abstract

Both cache directories and arrays waste considerable bandwidth that can be harnessed by using a CCDTAT which allows the cache directory and its arrays to respond to multiple concurrent cache accesses.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 39% of the total text.

Improving the Bandwidth of a Single Cache Directory and Array

      Both cache directories and arrays waste considerable bandwidth
that can be harnessed by using a CCDTAT which allows the cache
directory and its arrays to respond to multiple concurrent cache
accesses.

      In those caches which utilize a late select means of reducing
the the cache access time, it is of critical interest to observe two
features of the cache directory and the cache arrays:

1.  A similar waste of bandwidth occurs within the directory of the
    cache and the arrays of the cache.  In the arrays, multiple
    candidate DWs are accessed and only one will be used.  In the
    directory, multiple real address tags are concurrently accessed
    and, at most,one will be used.
2.  The concept of MRU within congruence class applies equally well
    to the real address tags as it does to the lines in the cache.

The significance of these observations is that inherent in any cache
is the ability to perform dual accesses to both the directory and the
arrays.  The central component of such a system is the CCDTAT.

      The CCDTAT is a table which associates with each congruence
class (CC) the DIRECTORY TAG (DT) that holds the MRU REAL ADDRESS TAG
of that congruence class and the ARRAY TAG (AT) of the ARRAY that
holds the first DW of the MRU line in this congruence class.  As both
these tags are updated simultaneously, the design of the machine can
make them equal.  Thus the bits maintained within the CCDTAT indicate
the position within both the directory arrays and the data arrays of
the MRU candidate for every access prior to directory lookup.

      Utilizing a cache directory that has the ability to respond to
different addresses sent to its different arrays, under a fairly
general set of conditions, a cache directory and its arrays can
respond to multiple concurrent accesses.

      As the CCDTAT associates with each CONGRUENCE CLASS, the
DIRECTORY TAG and the ARRAY TAG of the MRU line in that congruence
class, and given two accesses to different congruence classes, (One
of the accesses will be given a priority which is introduced merely
to break ties.)  a set of compatible candidate selections can be
generated which accomplishes all of the following:

1.  If the CCDTAT entries are different, then both MRU candidates
    (ADDRESS TAGS, DATA) will be chosen.

2.  The other candidates chosen are arbitrarily vis-a-vis MRU-LRU so
    the best choice is to asymmetrically assign candidates, choosing
    all other candidates for the priority access compatible with the
    first condition.

3.  In the event that the CCDTAT entry is the same for both
    candidates, the priority access performs a standard "late select"
    access.

The results of the lookup in the DLAT are used against the
appropriate ADDRESS TAGS derived from the directory, and a comparison
will result in the direction of the array output to its sink...