Browse Prior Art Database

Memory-Testing Mechanism for Computer Systems

IP.com Disclosure Number: IPCOM000104909D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 102K

Publishing Venue

IBM

Related People

Amini, IZ: AUTHOR [+3]

Abstract

Described is a hardware/software implementation to provide self-testing of large memories in computer systems during power-on-self-test (POST) operations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Memory-Testing Mechanism for Computer Systems

      Described is a hardware/software implementation to provide
self-testing of large memories in computer systems during
power-on-self-test (POST) operations.

      In prior art, memory testing of a computer involved the use of
microcode to write different patterns into each memory address and
then to read back from the same address.  If the patterns that were
read match the original patterns, then the memory was considered to
be functional.  This approach was useful in computers with small
memories, however, for computers having large memories POST became
time consuming and inefficient.

      The concept described herein provides a fast alternative by
combining the flexibility of the POST operation with a high-speed
hardware self-test.  The memory-testing mechanism consists of a set
of registers, address stepper logic, and data and address compare
logic.  A set of programmable registers is used to store programmable
address ranges and patterns for use in the memory testing.  In
addition to the programmable registers, a set of standard patterns is
provided in the pattern registers for default test operations.  A
minimum of two error registers allows the capturing of error data and
its corresponding address.  The figure shows a block diagram of the
registers and how they interface with the functional logic elements
of the mechanism.

The registers and how they are used are as follows:

COMMAND       - Specifies the operation and selects a pattern
register
BEGIN ADDRESS - Specifies the beginning address for memory test
END ADDRESS   - Specifies the ending address for memory test
PROG.  PATTERN - Stores the programmable pattern for testing
PATTERN 1     - Stores the built-in pattern 1
PATTERN 2     - Stores the built-in pattern 2
PATTERN 3     - Stores the built-in pattern 3
PATTERN 4     - Stores the built-in pattern 4
STATUS        - Stores the status upon the completion of testing
ERR DATA      - Stores the read-back data in error
ERR ADDRESS   - Stores the address of the erroneous data

o   The address stepper logic is used to provide the address of the
    next memory location that is to be tested.  This enables the
    logic t...