Browse Prior Art Database

Real Time Address Trace Reduction Using Translation Look-Aside Buffer or Cache

IP.com Disclosure Number: IPCOM000104920D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Duffield, NJ: AUTHOR [+3]

Abstract

Disclosed is a method to use a hardware facility already present in the processor hardware, e.g., translation look-aside buffer (TLB) or cache, to greatly reduce the address information that is needed to obtain a full address trace.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Real Time Address Trace Reduction Using Translation Look-Aside Buffer or Cache

      Disclosed is a method to use a hardware facility already
present in the processor hardware, e.g., translation look-aside
buffer (TLB) or cache, to greatly reduce the address information that
is needed to obtain a full address trace.

      By substituting the address to the hardware facility for the
actual address on hits to the facility, address trace information can
be reduced by a factor of 3 to 5, making it possible to trace all
accesses with a reasonable number of external hardware pins and
without slowing down the processor.  Post processing software can
recreate the full trace by simulating the hardware facility used to
reduce the trace information.

      The entire address only needs to be traced on accesses that get
a 'miss' in the hardware facility.  Given a miss takes enough cycles
to send out the entire address; no data would be lost, and the
processor would not have to be slowed down.  This address would then
be added to the simulated hardware facility by the post processing
software.  On hit accesses, only the portion of the address used to
access the hardware facility is needed.  These few bits are
sufficient for the post processing software to access the simulated
hardware facility, which would give the desired information about the
entire address being used.  If the hardware facility is set
associative, a few additional bits are needed on hits to indicate
which associativity class got the hit.  This is needed for the post
processing software to maintain the replacement information in the
simulated hardware facility.

      To maximize the usefulness of the trace information, the state
of the simulated hardware facility needs to be initialized to that of
the actual hardware facility when the trace was started.  This can be
done in two ways:

1.  Purge the hardware facility at the start of tracing.  This makes
    the hardware facility 'empty'.  It is easy for post processing
    software to initialize the simulated hardware facility to an
    'empty' state.
2.  Dump all entries in the hardware facility to the trace when
    tracing is started.  This informatio...