Browse Prior Art Database

Improving Chip I/O Effectiveness by Memory Address Encoding and Decoding

IP.com Disclosure Number: IPCOM000104921D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Chi, CH: AUTHOR [+2]

Abstract

Due to temporal and spatial properties of references, the bit pattern of references sent along the address bus(es) are highly predictable based on the history of the bit pattern of references that were sent in the past. Thus, it is possible to eliminate the redundant address information and to send only that address information that is really needed across the cache chip and the memory chip boundaries. The saved chip I/O bandwidth can then be used to either increase the data bus bandwidth or to reduce the cost of chip implementation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Improving Chip I/O Effectiveness by Memory Address Encoding and Decoding

      Due to temporal and spatial properties of references, the bit
pattern of references sent along the address bus(es) are highly
predictable based on the history of the bit pattern of references
that were sent in the past.  Thus, it is possible to eliminate the
redundant address information and to send only that address
information that is really needed across the cache chip and the
memory chip boundaries.  The saved chip I/O bandwidth can then be
used to either increase the data bus bandwidth or to reduce the cost
of chip implementation.

      This reduction of the address bus bandwidth can be achieved by
first encoding the reference address sent so that the address sent
across the cache chip boundary has only N' bits, where N' is less
than the length of the full address N.  After the memory chip
receives the encoded address, it decodes the address back to its
original N bits for further memory access.  The hardware to support
this is shown in the figure.  The cache line address to be sent to
the memory is divided into two portions: a higher-order bit portion
and a lower-order bit portion.  Only the higher-order bit portion is
encoded and decoded.  The lower- order bit portion of the reference
address will be sent directly to the memory system unchanged.
Encoding of the higher-order bit portion of the reference address is
done using a set associative lookup table.  The address is stored in
the lookup table (just like cache) inside the cache chip, and the...