Browse Prior Art Database

Forced Branching from the Sequencer

IP.com Disclosure Number: IPCOM000104930D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

East, RE: AUTHOR [+3]

Abstract

One problem with a single chip implementation of the RISC System/6000* architecture is the amount of function needed to be handled on a single chip. One way to fix this problem is to use a general-purpose coprocessor that can handle all the tasks not implemented in dedicated hardware. This coprocessor, called the Sequencer, takes care of tasks that are not handled by the other execution units. Some of the tasks handled by the Sequencer include all I/O processing, interrupt handling translation lookaside buffer

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 95% of the total text.

Forced Branching from the Sequencer

      One problem with a single chip implementation of the RISC
System/6000* architecture is the amount of function needed to be
handled on a single chip.  One way to fix this problem is to use a
general-purpose coprocessor that can handle all the tasks not
implemented in dedicated hardware.  This coprocessor, called the
Sequencer, takes care of tasks that are not handled by the other
execution units.  Some of the tasks handled by the Sequencer include
all I/O processing, interrupt handling translation lookaside buffer

(TLB) misses, real-time clock functions, and error handling.  While
servicing all of these requests, it may be necessary for the
processor to begin executing code in a different part of memory.  It
is the job of the Sequencer to redirect the program flow to the new
code section.

      Built into the hardware of the I/O Sequencer is the ability to
place data in the fixed-point virtual address register (VAR).  This
data can be the address for the new code location.  Once a new
address is placed in the VAR, the Sequencer signals the fixed-point
unit to start executing instructions at the memory location indicated
by the VAR.  By only using two microcode instructions, the Sequencer
is able to force the processor to branch to a new code location very
efficiently.

      By being able to redirect the fixed-point unit to any new code
location with the Sequencer, the processor is able to branch to the
interrupt...