Browse Prior Art Database

Method to Verify Chip-to-Chip Interconnect within a Hardware System

IP.com Disclosure Number: IPCOM000104938D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+3]

Abstract

Disclosed is a strategy for verifying the chip-to-chip interconnect within a given hardware system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 55% of the total text.

Method to Verify Chip-to-Chip Interconnect within a Hardware System

      Disclosed is a strategy for verifying the chip-to-chip
interconnect within a given hardware system.

      Identifying faults in the interconnect of chips within a system
is difficult and time consuming, especially in multi-chip modules
(MCMs).  Multi-chip modules contain multiple chips within a common
carrier.  Only inputs or outputs leaving the MCM are visible at the
external pins of the MCM.  Internal wires between chips cannot be
observed and tested directly.

      Using existing built-in hardware within the chips, a sequence
of commands can be issued to the chips to force the inter-chip
connections (ICCs) to be exercised.  The built-in hardware includes a
common on-chip processor (COP).  The COP can be used to initialize
the state of the chip and control the clocking of the chip itself.
COP commands exist to control the scanning of the boundary scan
string of a chip (FLUSH), to enable the output drivers of a chip
(OUTBND), to enable the input receivers of a chip (INBND) and to run
for a certain number of cycles (RUN_N).  The boundary scan string is
a set of latches that can drive and receive all of the outputs and
inputs, respectively, of a chip.  A chip-to-chip program called C2C
checks the ICCs of the MCM by issuing COP commands.  C2C chooses one
chip to drive its outputs and the remaining chips to receive the
corresponding inputs in order to check the ICCs.  The boundary...