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Data Transfer Through Cross-Bar Matrix Using Parallel, Asynchronous Data Paths

IP.com Disclosure Number: IPCOM000104942D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Georgiou, CJ: AUTHOR [+4]

Abstract

Disclosed is a method of transferring very high-speed data through a crossbar switch by converting the parallel, synchronous data at a source port into two or more serial, asynchronous data streams which are switched through corresponding crosspoint matrices, and recapturing the data using phase-alignment techniques at the destination. The outputs of the phase-aligners are recombined into a common parallel, synchronized data path.

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Data Transfer Through Cross-Bar Matrix Using Parallel, Asynchronous Data Paths

      Disclosed is a method of transferring very high-speed data
through a crossbar switch by converting the parallel, synchronous
data at a source port into two or more serial, asynchronous data
streams which are switched through corresponding crosspoint matrices,
and recapturing the data using phase-alignment techniques at the
destination.  The outputs of the phase-aligners are recombined into a
common parallel, synchronized data path.

      The concept of transmitting asynchronous data streams has been
described.  At very high data rates, a single high speed serial data
stream puts significant demands on the technology of the matrix
chip(s), packaging, interconnects, and the port-interface functions
(i.e., the phase-aligner and multiplexers/ demultiplexers).  On the
other hand, using parallel synchronous data flow puts many other
demands on the technology (such as, for example, the need for a high
number of I/O's precise clocking network, limited port expansion,
etc.)  This article discloses a compromise to these approaches.

      In a prior-art approach, asynchronous data are clocked out of a
switch source port and are passed unclocked through the crosspoint
matrix to a switch destination port.  At the destination port, the
data are re-aligned with the clock generated from a phase-aligner
function.  In order to reduce the demands on the implementation
technology of the crosspoint chip (or array of crosspoint chips), the
packaging, and the phase-aligner, the approach illustrated in the
figure is suggested.

      In this approach, a 10bit...