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L2 Latch Design for Detecting Transition Faults

IP.com Disclosure Number: IPCOM000104958D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 67K

Publishing Venue

IBM

Related People

Koo, C: AUTHOR [+2]

Abstract

To test a transient fault at system speed, two test patterns are needed. The first pattern initializes the logic network, and the second pattern tests a transient fault, if present.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

L2 Latch Design for Detecting Transition Faults

      To test a transient fault at system speed, two test patterns
are needed.  The first pattern initializes the logic network, and the
second pattern tests a transient fault, if present.

      Scanning in the second pattern at system speed may not be
possible for all transient faults.  To assure testing of every
transient fault, two methods are proposed.

      Figure 1 shows a typical conventional SRL (Shift Register
Latch) comprised of latches L1 and L2.  L1 accepts system data (D)
with the system clock (C) or scan data (SD) with the scan clock (A).
With neither clock on, L1 holds its value.  L2 accepts the L1 output
with the B clock and holds its value in the absence of the B clock.

      The first proposed method (Figure 2) adds a test clock (T) to
L2 as well as a select signal (S).  The T clock replaces the B clock
during the test cycle and permits the selected L2 to be inverted to
effect a desired transition in the logic network which it enters.

      The second method (Figure 3) leaves the clocking system intact
but adds additional logic affecting L1.  During a test cycle, a T
signal permits the complement L2 signal to enter L1 by means of the C
clock if the SRL is selected and the true L2 if not selected.

      Figure 4 shows the operation of the first method for testing an
AND block.  After initialization, the two SRLs controlling the inputs
to the AND are 11 with the AND output sw...