Browse Prior Art Database

Method to Control the Actual Implementation of a High-Level Design Language

IP.com Disclosure Number: IPCOM000104964D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Golla, RT: AUTHOR

Abstract

Disclosed is a method for controlling the exact technology-dependent implementation of a high-level design language in a given CMOS technology.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method to Control the Actual Implementation of a High-Level Design Language

      Disclosed is a method for controlling the exact
technology-dependent implementation of a high-level design language
in a given CMOS technology.

      Designers do not have explicit control over the implementation
of designs written in a high-level design language (HDL).  An HDL is
technology-independent.  HDLs do not specify the actual
implementation of a design.  The actual implementation of a design is
often determined by synthesis programs run by the designer.  These
programs generally run in batch mode and do not support interaction
with the designer.  Hence, the designer does not have explicit
control over the implementation of a design.  Such control is often
required in order to meet space and timing constraints during the
chip design process.

      A preprocessor called STRUCTURE PRESERVE (SP) allows the
designer to actually control the implementation of a HDL design.  As
shown in Figure 1, SP reads in a HDL design specified by the
designer, an EQUA TIONS file and a PINS file.  These files are used
to map the designer's equations directly to equivalent devices in a
given technology.  The EQUATIONS file contains a logical boolean
equation for each of the devices present in a given technology.  Each
of these equations is stored in memory by SP in a standard format.
This format contains information about the number of terms within the
equation, the depth of each term, and the various ways that the
equation can be represented in the HDL.  The PINS file is also read
and stored in memory by SP.  The PINS file contains information on
how to generate low-level device calls within the HDL for each of t...