Browse Prior Art Database

Across-the-Bus Testing of Adapter Functions during Intitial Program Load

IP.com Disclosure Number: IPCOM000104966D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 148K

Publishing Venue

IBM

Related People

Harper, SM: AUTHOR [+2]

Abstract

This article discloses a process to test an across-the-bus function of an intelligent adapter. This process elliminates the need for additional code executing on the host system during Initial Program Load (IPL).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 41% of the total text.

Across-the-Bus Testing of Adapter Functions during Intitial Program Load

      This article discloses a process to test an across-the-bus
function of an intelligent adapter.  This process elliminates the
need for additional code executing on the host system during Initial
Program Load (IPL).

      An intelligent adapter can be defined as having a
microprocessor that can execute instructions.  Intelligent adapters
commonly have Read-Only Memory (ROM) present with Adapter Power
On-Self Test (APOST) code contained in the ROM.

      APOST is executed when power is applied to the adapter or the
adapter is given a reset command by software executing on the system.
APOST performs a series of tests to exercise the hardware contained
on the adapter.  This testing is critical to ensure that the adapter
is working correctly before it is brought into operation.

      While APOST tests the subsystems contained on the card, it has
a difficult, if not impossible time, testing functionality across the
system bus.  Code executing from an adapter's processor is limited in
that it cannot access or control system level resources in most
cases.  Therefore, it is impossible to test out the adapter
adequately unless there is interaction with code executing on the
system to test the system/adapter interfaces.

      This testing is needed to ensure that critical boundary
interfaces are tested before the adapter is put into operation.
Typically, code (such as a diagnostics package) must be running on
the system to do this type of testing.  However, to do this operation
during a normal Initial Program Load (IPL) sequence is time consuming
and adds complexity to the overall process.  Ideally, this testing
would be done during the normal course of operations to bring the
adapter on-line, thus requiring no additional steps or interaction
with code running on the system.

      This problem manifests itself in the area of processors with
cache such as Intel's 80486.  In order to test out the advanced
functions provided by the processor in an adapter environment, it is
necessary to interact in a controlled manner with code running on the
system.

      The on-chip cache is high speed memory that contains copies of
the most recently accessed instructions or data.  Cached information
can be accessed much more quickly than it could be from standard
DRAM, speeding up execution time.  For normal operation the processor
can be set-up to cache various portions of memory.

      The 80486 processor provides a "snoop" function which is
necessary when an alternate bus master can alter adapter RAM.
Snooping ensures data coherency between cache memory and adapter
memory by identifying writes to external memory that is also
contained in the internal cache.

      It is critical that the snooping function is tested to ensure
proper operation of a Busmaster adapter.  If snooping isn't
functioning properly, cache invalidation may not occu...