Browse Prior Art Database

Amendable Memory System

IP.com Disclosure Number: IPCOM000104976D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Cheng, FM: AUTHOR [+5]

Abstract

Disclosed is a logic design which provides a flexible interface between two elements. The design enables one element to connect to more than one version of a second element. The disclosed design further allows the interface to be programmed for each version of the second element to achieve the maximum performance from each version. The design uses programmable registers to control data path steering and the timing of inter-element control signals.

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This is the abbreviated version, containing approximately 69% of the total text.

Amendable Memory System

      Disclosed is a logic design which provides a flexible interface
between two elements.  The design enables one element to connect to
more than one version of a second element.  The disclosed design
further allows the interface to be programmed for each version of the
second element to achieve the maximum performance from each version.
The design uses programmable registers to control data path steering
and the timing of inter-element control signals.

      A typical application is the interface between a system element
and its memory elements, which may vary to optimize machine
price/performance.  The figure illustrates a four element memory
design which allows for a second memory element version which
transfers data at one half the rate of the faster memory.  Each
version of memory has the same bus width across the interface.  Data
is toggled between two slower memory elements to achieve the faster
memory data rate.  The system elements uses half of its data paths
internally when the slower memory is installed.

      The data rate is stored in to the Programmable Control Register
(PCR), which is used to select the appropriate data paths between the
system element and memory.  The dashed lines in the figure illustrate
the data paths which are enabled on alternate data transfer cycles
when the half-rate memory is installed.  In this mode, the normal
system input signals into the odd- numbered Data Out Registers are
not activ...