Browse Prior Art Database

Conditional Register Putaway

IP.com Disclosure Number: IPCOM000104981D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Frey, BG: AUTHOR

Abstract

In CISC architectures and many RISC architectures, there are instructions which take many cycles to execute while not fully utilizing the parallelism available in their respective processor implementations. A subset of these instructions produces a characteristic, predictable result upon normal completion, which is placed in a register. Interrupts, exceptions, and other abnormal completions are often the only sources of other results. In other cases, the value of the result is merely reliable in a statistical sense. That the value in the register properly reflects the execution of the instruction is clearly a requirement. Putting that value into the register at the END of execution greatly restricts the potential overlap that could take place between the long-running instruction and those following it.

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This is the abbreviated version, containing approximately 52% of the total text.

Conditional Register Putaway

      In CISC architectures and many RISC architectures, there are
instructions which take many cycles to execute while not fully
utilizing the parallelism available in their respective processor
implementations.  A subset of these instructions produces a
characteristic, predictable result upon normal completion, which is
placed in a register.  Interrupts, exceptions, and other abnormal
completions are often the only sources of other results.  In other
cases, the value of the result is merely reliable in a statistical
sense.  That the value in the register properly reflects the
execution of the instruction is clearly a requirement.  Putting that
value into the register at the END of execution greatly restricts the
potential overlap that could take place between the long-running
instruction and those following it.

      To realize some of the potential overlap between the
long-running instruction and those following it, the processor can be
designed to put a predicted result into the register very early in
the instruction execution.  The result is conditional until proven
correct or incorrect when the instruction's execution is completed.
Subsequent instructions which operate on this register value can be
decoded and execute conditionally until the value is validated.  If
the long instruction completes as expected, the early execution of
the subsequent instructions is transparent to the external world.  If
the instruction completes with an unexpected value, the subsequent
instructions can be removed from the pipeline without modifying any
visible processor state.  The result is increased performance due to
the optimization of the more common case of execution.

      To implement this technique can be anywhere from very simple to
quite complex.  In a processor wh...