Browse Prior Art Database

Central Processing Unit Lookahead Logic for Video Memory

IP.com Disclosure Number: IPCOM000105008D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Thompson, SP: AUTHOR

Abstract

The performance of a video memory is improved by using an address latch signal ADL as a lookahead signal instead of using a command signal CMD to transfer data between a central processing unit CPU and the video memory when a stat machine is used to perform arbitration between the CPU and the and a cathode ray tube CRT screen refresh function.

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Central Processing Unit Lookahead Logic for Video Memory

      The performance of a video memory is improved by using an
address latch signal ADL as a lookahead signal instead of using a
command signal CMD to transfer data between a central processing unit
CPU and the video memory when a stat machine is used to perform
arbitration between the CPU and the and a cathode ray tube CRT screen
refresh function.

      The state machine, an arbiter, uses the ADL signal, which
occurs sooner in time in the bus cycle than the command signal CMD,
to determine if a CPU memory operation is to take place.  Responding
to the ADI signal, any CRT cycles in progress are completed and
precharge operations are performed on memory devices.  The use of the
ADL signal also prevents the state machine from starting unnecessary
CRT memory cycles that would cause the CPU to wait.  Since data is
not transferred to or from the CPU until the CMD signal goes active,
the state machine waits until the CMD signal does not follow the ADL
signal before the CRT requires data, the system allows the state
machine to perform a CRT cycle during this time.  By allowing the
arbiter to finish up pending cycles, perform precharge operations and
eliminate unnecessary cycles, the system provides improved CPU video
memory performance.

      Fig. 1 shows the system configuration wherein the arbiter
determines whether the CRT or the CPU gains access to the memory
through the memory cycle generator.  The memory cycle generator and
the arbiter operate as two separat...