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Browse Prior Art Database

Sub Lithographic Reliable Isolation Scheme for High Density Drams

IP.com Disclosure Number: IPCOM000105010D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 84K

Publishing Venue

IBM

Related People

Rajeevakumar, TV: AUTHOR

Abstract

Trench isolations have been used for CMOS device isolation in lieu of LOCOS. It is believed that trench isolation is superior to LOCOS because of the 'bird's beak' associated with LOCOS [*]. However, trench isolation such as shallow trench isolation (STI) also has drawbacks. For example, with decreasing trench opening, it is difficult to fill the isolation trench with oxide without voids. A new isolation scheme where sub-lithographic trench isolation is used to significantly save cell area is proposed here. The proposed scheme is more reliable and denser than the conventional ones.

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Sub Lithographic Reliable Isolation Scheme for High Density Drams

      Trench isolations have been used for CMOS device isolation in
lieu of LOCOS.  It is believed that trench isolation is superior to
LOCOS because of the 'bird's beak' associated  with LOCOS [*].
However, trench isolation such as shallow trench isolation (STI) also
has drawbacks.  For example, with decreasing trench opening, it is
difficult to fill the isolation trench with oxide without voids.  A
new isolation scheme where sub-lithographic trench isolation is used
to significantly save cell area is proposed here.  The proposed
scheme is more reliable and denser than the conventional ones.

      Fig. 1 shows the schematic layout of a DRAM cell array
illustrating how sub-lithographic isolation reduces cell area.  The
horizontal isolation lines provide isolation between devices.  The
vertical isolation lines provide the isolation between storage nodes.
In the array, depending on the cell structure, one lithographic
square or more, cell area can be reduced, if sub-lithographic spacing
between bitlines is also used.  Fig. 1 also schematically shows the
mask needed to fabricate the sub-lithographic isolation trench.  For
the cell example shown in Fig. 1, the reduction in cell area is about
2 lithographic squares.  Fig. 2 schematically illustrates the
vertical cross-section of the isolation structure in the array.  The
sub-lithographic shallow trenches are lined with ONO dielectric and
filled with polysilicon of the same polarity as that of the well.
The polyfill inside the trench is contacted to the substrate.  An
oxide cap is plac...