Browse Prior Art Database

Processor-Lock-Out-Free Bus Arbitration Mechanism

IP.com Disclosure Number: IPCOM000105012D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Nakada, T: AUTHOR [+3]

Abstract

Disclosed is a Bus arbitration mechanism for shared-bus multiprocessor systems. This mechanism provides an efficient Bus arbitration that does not incur the problem of processor lock-out.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 55% of the total text.

Processor-Lock-Out-Free Bus Arbitration Mechanism

      Disclosed is a Bus arbitration mechanism for shared-bus
multiprocessor systems.  This mechanism provides an efficient Bus
arbitration that does not incur the problem of processor lock-out.

      In shared-bus multiprocessor systems, an atomic operation
implemented by a read-modify-write operation is essential for
realizing synchronization between processors.  To distinguish
read-modify-write bus operations from the normal ones, Intel's i486
microprocessor has a signal called LOCK#.  The i486 asserts LOCK# to
indicate that the read-modify-write operation is in progress.  During
this operation, the processor can read and modify a variable in
external memory and be assured that the variable will not be accessed
by other processors between the read and write.

      LOCK# becomes active with the address and bus command signals
at the beginning of the first read cycle and remains active until the
end of the last write cycle.  However, the i486 has a hardware
feature that LOCK# does not become inactive between two or more
consecutive read-modify-write operations.  Since LOCK# remains active
between back-to-back read-modify-write operations, the shared bus
cannot be relinquished and therefore cannot be used by any other
processors.  This situation is called dead-lock.

      The disclosed mechanism solves the problem by using a simple
additional hardware mechanism.  The Figure shows a block diagram of...