Browse Prior Art Database

N-P-N Transistor with Hole Injection Barriers

IP.com Disclosure Number: IPCOM000105018D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 64K

Publishing Venue

IBM

Related People

Hodgson, RT: AUTHOR [+2]

Abstract

Disclosed is an N-P-N transistor structure made on a substrate with MBE or CVD grown layers, and patterned by normal silicon technology.

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N-P-N Transistor with Hole Injection Barriers

                            FIGURES 1 & 2

      Disclosed is an N-P-N transistor structure made on a substrate
with MBE or CVD grown layers, and patterned by normal silicon
technology.

      The silicon substrate has layers grown by MBE or CVD as shown
in Fig. 1.  An n type silicon substrate 1 has a p+ layer 2, a thin
150 A  thick pseudomorphic layer of undoped GaAs 3, and an n
type silicon layer 4 grown by normal chemical vapor deposition (CVD)
or molecular beam epitaxy (MBE) techniques.  Metal emitter electrodes
7 are deposited, and boron is implanted to form heavily boron doped
(p+) regions 5.  The emitter electrode 7 is etched back and metal
contact 6to base region 5 is made from the structure sketched in Fig.
2.  The band diagram of the device with no voltage applied is
sketched in Fig. 3a, and the band diagram with a voltage applied from
emitter 4 to collector 1 is sketched in Fig. 3b.
                           FIGURES 3a & 3b

1.  The undoped GaAs layer forms a barrier to prevent hold injection
    from the base to the collector.

2.  The device has lower parasitic base emitter current than a
    Si(n)-SiGe(p)-Si(n) heterojunction transistor.

3.  At the typical times and temperatures needed to activate the
    boron implant (850C for 10 sec) the silicon does not diffuse and
    dope the GaAs[1].  In addition, there are no p type dopants for
...