Browse Prior Art Database

Smart Burst - Dual Bus Control for Improved Personal Computer Performance

IP.com Disclosure Number: IPCOM000105022D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Capps, LB: AUTHOR [+8]

Abstract

Described is an architectural logic implementation to provide "Smart Burst" (SB) dual bus control to improve personal computer (PC) performance by providing a means of reducing the number of processor accesses to memory during bus master burst operations.

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Smart Burst - Dual Bus Control for Improved Personal Computer Performance

      Described is an architectural logic implementation to provide
"Smart Burst" (SB) dual bus control to improve personal computer (PC)
performance by providing a means of reducing the number of processor
accesses to memory during bus master burst operations.

      Typically, a dual bus used with high speed processors
represents a balanced approach between central processing unit (CPU)
and the Micro Channel* (MC) bus masters.  Concurrent cycle operations
rely on the CPU cache to provide a substantial bandwidth for the CPU
on the local bus.  This frees the system/MC bus and the planar memory
for bus master operations.  However, the speed of the CPU operates at
a higher speed than the dual bus.  This can cause cache misses as
related to the memory controller and the arbiter.  As the relative
number of cache misses increases, the number of CPU planar memory
accesses will increase.  This can cause interruptions to the
system/MC bus cycles relative to the planar memory.  During a bus
master burst cycle, the increased activity of the CPU into planar
memory will increase the number of page miss cycles for both the
bursting bus master and the CPU, also known as "thrashing".
Thrashing will reduce the overall throughput of the system because
the forced page misses requires extra cycles to complete the accesses
to memory.

      The concept described herein provides SB control to improve
dual bus cycles to planar memory.  The SB provides dynamic control of
the CPU memory bandwidth by adjusting to the bus master activity.
The SB can be disabled by means of software control to provide normal
interle...