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Updating Unique Registers in a Duel Execution Unit Design

IP.com Disclosure Number: IPCOM000105032D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Spencer, AK: AUTHOR

Abstract

In a Fixed Point dual execution unit processor design there are two registers that cannot be duplicated due to the architectural defini tions. The registers are the Fixed Point Exception register (XER) and the Multiply/ Quotient Register (MQ). Please see Figures 1 and 2 for a diagram of these two registers.

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Updating Unique Registers in a Duel Execution Unit Design

      In a Fixed Point dual execution unit processor design there are
two registers that cannot be duplicated due to the architectural
defini tions.  The registers are the Fixed Point Exception register
(XER) and the Multiply/ Quotient Register (MQ).  Please see Figures 1
and 2 for a diagram of these two registers.

      Both of these registers can be written to by both execution
units in one cycle.  So how do we ensure that the correct result is
written to the register?  The XER register has two sources: The `A'
unit S-Buffer and the `B' unit S-Buffer.  The MQ register has six
sources: The MQ backout register, the multiply and divide MQ mux, the
`B' unit Rotator, and S-Buffer, the `A' unit Rotator and S-Buffer.
As we can see we have multiple sources for each of these registers
and so they are implemented as multi-port registers.

      The solution to this problems is quite elegant in that it
requires no additional control logic but makes use of one of the
design elements of our CMOS-4S multiport registers.  These registers
have priority encoded select logic.  This logic prevents the contents
of the register from turning into trash if two or more selects
signals are active in a given cycle.

      In the Fixed Point chip when two instructions execute in one
cycle, the second execution unit executes the last instruction while
the first execution unit executes the first.  Thus if both
instructions update the same register then the value from the last
instruction must be reflected in the final result.  This always mean
that the second execution unit will overwrite any value written by
the first unit.  The solution is to use the priority encoding build
into the registers to our advantage by always connecting the input
from the second unit to lower numbered ports than from the first
unit.

      Lets look at the XER in Fig. 1 in more detail.  Here, port 0
has the S1_BUFFER from the second unit connected, while port 1 has
the S0_BUFFER from the first unit connected t...