Browse Prior Art Database

Multiple Execution Cache Directory Swapping

IP.com Disclosure Number: IPCOM000105038D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Ray, DS: AUTHOR [+2]

Abstract

A method for efficiently using multiple-execution units with dual ported caches is disclosed. Cycles are saved by directing an instruction to another execution unit when a particular data-cache port is 'busy'.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multiple Execution Cache Directory Swapping

      A method for efficiently using multiple-execution units with
dual ported caches is disclosed.  Cycles are saved by directing an
instruction to another execution unit when a particular data-cache
port is 'busy'.

      In multiple execution unit designs with multi-ported caches and
cache directories, it is desired to get the most performance and
usage out of the multi-ported units.  In the drawing shown, a two
port direc tory and cache allows for up to two loads and/or stores to
access the cache as long as there is a 'hit' in the cache.  In this
implementation, when there is a 'miss' in the cache directory, that
cache directory is busy doing a reload of the cache and is not
accessible to any more loads and stores until the new line has been
reloaded.

      However, the other unit may continue processing cache requests
as long as they are 'hits in the cache' until a miss occurs.  Yet,
this requires that good scheduling of instructions, (i. e., put loads
and stores into the unit which is not busy doing a reload), such that
the cache is utilized at its best efficiency.  Unfortunately,
scheduling of instruc tions is done the cycle before execution and
detection of cache busy is done during execution.  Therefore, a
effective means of utilizing the caches is needed.

      The Figure shows a double execution unit with dual ported cache
directories and cache arrays.  In this implementation, consider the
following instruction sequence:

  ld1          ;misses in cache directo...