Browse Prior Art Database

Open-Short Circuit Self Test

IP.com Disclosure Number: IPCOM000105043D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Chin, AL: AUTHOR [+2]

Abstract

This article describes the use of very large scale integration (VLSI) boundary scan latches to utilize an available VLSI feature to automate the manual debug activities associated with the development process of any system or card that uses VLSI.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Open-Short Circuit Self Test

      This article describes the use of very large scale integration
(VLSI) boundary scan latches to utilize an available VLSI feature to
automate the manual debug activities associated with the development
process of any system or card that uses VLSI.

      The boundary scan latches are connected inside the VLSI module
and outside the VLSI module to the system board.  Each latch is
capable of latching a data or address or control bit that is
presented on the physical module Input/Output pin.  This same latch
is also connected inside the module in such a way that it is a bit of
a shift register whose content can be serially shifted/clocked in or
out through the module designated test pin.

      In the system functional procedure all communication between
the system processor unit and the VLSI are write or read commands for
controlling system function.  The processor performs these commands
by first presenting a combination of zero or one bits at the VLSI
pins via the Data, Address bus (see drawing:  D/A/C BIT # pins), then
pulsing one of the control pins to clock in the data and address
information.  If any of those solder connections is open, the command
that the processor tries to write to the VLSI module is not what the
VLSI module internal logic received and interpreted (system
malfunction).  For normal system implementation practice, the VLSI
module built in test features are not used and are disabled or not
supported.  During system operation, the boundary scan latches are
transparent to the system.

      In the VLSI factory scan test procedure there are a set of test
pins reserved on each VLSI module for the factory to test for good
module prior to delivery to manufacturing for installation.  These
scan test pins are used in the following manner:  Similar to the
system functional procedure, the factory test fixt...