Browse Prior Art Database

Reduce Branch Latency in Multi-Unit Computer with Branch Unit

IP.com Disclosure Number: IPCOM000105050D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 61K

Publishing Venue

IBM

Related People

Ray, DS: AUTHOR [+2]

Abstract

A method for reducing branch latency in multi-execution unit organizations with branch units is disclosed. Cycles are saved when branch resolution logic is implemented in the execution units.

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This is the abbreviated version, containing approximately 87% of the total text.

Reduce Branch Latency in Multi-Unit Computer with Branch Unit

      A method for reducing branch latency in multi-execution unit
organizations with branch units is disclosed.  Cycles are saved when
branch resolution logic is implemented in the execution units.

      Machine Organizations with a Branch unit and more than one
execution unit have a typical latency problem when branches are
waiting to be resolved.  In particular, an instruction stream like:

    cmp      ;puts condition code results in condition register
    brc      ;branches conditionally of condition register
    add      ;next instruction after brance (either target or
             ; sequential depending on branch prediction)
must wait an extra cycle when executed on a machine as show in Fig.
1.  In this organization, if the compare is executed in the left
unit, the add must wait in the right unit until the condition codes
got to the branch unit and get latched.  The next cycle, the branch
unit control logic tells the execution control logic whether or not
to let the right execution unit execute.

      Fig. 2 shows an organization which reduces this branch latency
by one cycle.  In this organization, the branch unit sends the
execution unit enough information, (i.e., which condition code bit to
look at, execute or not if that bit is a one or a zero), to determine
whether or not to execute the add in the right unit.

      Therefore, when the compare...