Browse Prior Art Database

New PMOS Pull-Up Circuit for Dual-Power Supply

IP.com Disclosure Number: IPCOM000105059D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 75K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+2]

Abstract

Disclosed is a new data output driver using PMOS pull-up devices. It uses two stacked PMOS devices with floating n-wells as a prior-art circuit does [*], but the stacked PMOS devices are operated in the two different modes, depending on the power supply voltage. Thus, the new data output driver can be used without a regulator for dual power supply.

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This is the abbreviated version, containing approximately 52% of the total text.

New PMOS Pull-Up Circuit for Dual-Power Supply

      Disclosed  is  a  new  data output driver using PMOS pull-up
devices.  It uses two stacked  PMOS  devices  with  floating n-wells
as  a  prior-art  circuit does [*], but the stacked PMOS devices  are
operated  in  the  two  different  modes, depending  on  the power
supply voltage.  Thus, the new data output driver can be used without
a regulator for dual power supply.

      The invention is schematically shown in Figs. 1 and  2.  Fig. 1
shows  the pull-up circuit.  It is composed of three stages of
pull-up circuit.  Fig. 2 shows the control circuit for the pull-up
circuit  shown in Fig. 1.  The  circuit operates as follows:

      During  standby  (or  in  high-Z state):   With OEB and
DRIVEHIGHB high, the nodes 1 and B in Fig. 2  are  high  and low,
respectively.    The  high  signal  at  the  node 1 is inverted by
the three inverters I2, I7,  and  I8  to  a  low signal,  which  is
applied to the gate of QN1.  It turns QN1 off and the node A floats.

      Referring to Fig. 1, a low  condition  at  the  node  B turns
QP1Y  on,  which makes the drain and the gate of QP1X shorted
together.  With DRIVEHIGHB and OEB high, the node  5 is  high and
keeps QP1 off.  The high condition at the node 5 is also applied to
QP2 and QP3 through the inverters I4, I2, I3 and the nand gate NN1,
keeping QP2 and  QP3  off.    Note also  that  the gates of the QP1,
QP2, and QP3 in Fig. 1 are always at the same voltage as VCCOCD which
is  supplied ...