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Fast MESFET with Non-Critical Alignment and No High Temperature Processing

IP.com Disclosure Number: IPCOM000105064D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 127K

Publishing Venue

IBM

Related People

Batstone, JL: AUTHOR [+3]

Abstract

Disclosed is a novel transistor structure using processing from both sides of a very thin (3000A) semiconductor. No implantations are necessary, and no high temperature processing is needed. Ohmic contacts are made to unpinned GaAs so that the n+ ohmic contacts are not necessary for the metal semiconductor contacts.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Fast MESFET with Non-Critical Alignment and No High Temperature Processing

      Disclosed is a novel transistor structure  using processing
from both sides of a very thin (3000A) semiconductor.  No
implantations are necessary, and no high temperature processing is
needed.  Ohmic contacts are made to unpinned GaAs so that the n+
ohmic contacts are not necessary for the metal semiconductor
contacts.

      The device is constructed as described in the figures.  A GaAs
substrate 1 has a number of layers grown on it by normal MBE or CVD
techniques as shown in Fig. 1.  A first layer 2 is a normal GaAs
buffer layer, layer 3 is an AlAs layer which will be sacrificed at a
later step, layer 4 is the Si doped GaAs layer which will be used for
devices, and layer 5 is a thin layer of As, which protects the
surface of the GaAs when the structure sketched in Fig. 1 is removed
from the MBE or CVD growth chamber and coated with photoresist for
the next step.

      A lift off photoresist coating is spun on, exposed, and
developed to give the structure sketched in Fig. 2.  The two layers
of the photoresist, 6 & 7, are used as a lift off mask in the
evaporation of metal in the next step.

      The patterned wafer of figure 2 is introduced into a UHV metal
evaporator, and the As unprotected by the photoresist is driven off
by thermal evaporation, leaving the GaAs surface unpinned.  Metal
evaporated on to this surface is now in good ohmic contact with the
Si  doped top layer of the wafer, without the necessity of forming a
patterned  n++ layer by the normal implantation and thermal annealing
process.  500 A  of Al evaporated at 80K will form low Schottky
barrier source and drain ohmic contacts.  The same features could be
made by first evaporating the aluminum metal uniformly over the
substrate while the wafer was still in the growth chamber,
subsequently patterning the metal.

      After metallization, the structure is removed from the vacuum
system and the photoresist material and overlying metal are removed.
Further insulator and metal layers are deposited and patterned in
ways well known in the art.  Aluminum ohmic contacts 8A and 8B,
insulator material 9, and metal lines 10 are built up.

      The substrate with its patterned metal lines is then coated
with a suitable polymer so that the polymer film is in tension, the
semiconductor layers in compression, The wafer could be joined to
another carrier 11 in a "flip chip" configuration.  Electrical
contact could or could not be made to the carrier., as the case may
be.  When the GaAs substrate and the adjoined chip carrier are
immersed in Hf or HCl, the AlAs...