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Time-Controlled Three-Stage Pull-Down Circuit with Improved Performance

IP.com Disclosure Number: IPCOM000105073D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+2]

Abstract

Disclosed is a new pull-down circuit for TTL-compatible data output buffer using NMOS devices. It is composed of three stages of pull-down circuit. The second stage, which is largest, is turned off after a fixed time interval. By shutting the second-stage off, the under- and over-shooting of the output node during load pull-down is improved as well as the bouncing of the on-chip ground node.

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Time-Controlled Three-Stage Pull-Down Circuit with Improved Performance

      Disclosed is a new pull-down circuit for TTL-compatible data
output  buffer  using NMOS devices.  It is composed of three stages
of pull-down circuit.  The  second  stage,  which  is largest,  is
turned  off  after a fixed time interval.   By shutting the
second-stage off, the under- and  over-shooting of the output node
during load pull-down is improved as well as the bouncing of the
on-chip ground node.

      The  circuit is schematically shown in the figure.  The major
difference of this circuit from the prior-art  circuit is  the added
control provided to the second-stage pull-down circuit, QN2.  The
circuit operates as follows.

      During standby (or in high-Z state):    With  OEA1  and OEA2
low,  QN1X, QN2X, and QN3X are off.  OEB and DRIVELOWB are all high
and the output node 5 of the NOR  gate  NR1  is low.  This, in turn,
makes the nodes Q and 9 low.  Thus, QN1, QN2, and QN3 are all off.

      During  pull-down:  With OEA1 and OEA2 changed to high, QN1X,
QN2X, and QN3X are on.  OEB and DRIVELOWB become  low, activating
the  NOR gate NR1.  The node 5 goes high, turning on QN1.  This
positive going signal at the node 5 generates a positive pulse at the
node Q by the positive  edge-triggered single-shot  pulse  generator
shown in the inset of Fig. 2.  The width of the pulse is primarily
determined by the  delay chain  composed  of  the  inverters  X1
through  X7 and pad capacitors.  Also, the high signal at the node 5
forces  the node  9  to  go  high,  turning  on QN3.  Inverters and
delay chains are arranged so that QN1, QN2, and and QN3 are turned on
in  sequence  with  a...