Browse Prior Art Database

Modular Processing System-RISC/370 Processor Design

IP.com Disclosure Number: IPCOM000105074D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 170K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+2]

Abstract

A single chip design for a major subset of the instructions used by MVS systems needs a means to execute all instructions. An analysis of the alternatives shows that a design modelled on 4 such chips sharing a fifth chips ability to execute all the the instructions not within the single chip's capability represents a reasonable alternative if certain cache related problems can be overcome.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 29% of the total text.

Modular Processing System-RISC/370 Processor Design

      A single chip design for a major subset of the instructions
used by MVS systems needs a means to execute all instructions.  An
analysis of the alternatives shows that a design modelled on 4 such
chips sharing a fifth chips ability to execute all the the
instructions not within the single chip's capability represents a
reasonable alternative if certain cache related problems can be
overcome.

      Within the S/370 instructions set there are both simple and
complex instructions.  There are instruction that can be executed in
a single execution cycle and there are instruction which require
multiple cycles to execute.  Beyond this dichotomy there are
instructions which fetch all their operands from registers and
instructions that fetch their operands from memory.  It is possible
to consider a RISC (Reduced Instruction Set Computer) which has
optimized its design in a manner similar to micro-processors.  All
instructions can be decoded and executed in a single cycle and the
only instructions which access memory are simple LOAD, simple STORE,
and BRANCH instruction.  A mapping of the single cycle execution
instructions onto such a design might be called RISC/370 and would
look somewhat like the following schematic:

        INSTRUCTION                          .
             |                               .
             |                               .
          PRIMARY                        RESIDUAL
 COM <-- DECODER ----------| -----------CONTROLS _
 PLEX      DOES             |            SI/RS/BC
 OPS     TRUE RR         SECONDARY     INSTRUCTIONS
           LOAD            DECODER           .
             |              V                .
             |        *****************      . B
             V        *     ALU       *      . U
       ****************************** *      . S
       *                            * *      .
       *   GPR AND ALU              * --------
       *                            *
       ******************************

 A SECOND ALU AND GREATER BANDWIDTH FOR GPR ACCESS
 ALLOWS THE SECOND DECODER TO OPERATE IN PARALLEL
 WITH THE FIRST DECODER DECREASING CPI IMPACT OF
 INSTRUCTION SPLITTING

Within this schematic let us consider the fate of those instructions
which are considered too complex to be performed within the data path
of the RISC machine and will be performed off-chip.

      Let us call the chip that executes the simple instructions the
I-CHIP and the chip that executes the complex instructions the
...