Browse Prior Art Database

Programmable System Clock

IP.com Disclosure Number: IPCOM000105080D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 70K

Publishing Venue

IBM

Related People

Clement, JY: AUTHOR [+2]

Abstract

Disclosed is a system which generates entirely programmable signals (clocks,controls,etc.). These signals can be reprogrammed at any time. The automatic power on programming can be done during the LSSD initial ization, by EPROM etc.

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Programmable System Clock

      Disclosed is a system which generates entirely programmable
signals (clocks,controls,etc.).  These signals can be reprogrammed at
any time.  The automatic power on programming can be done during the
LSSD initial ization, by EPROM etc.

      The innovation of this system is the use, for signal
generation, of "elementary pulses" and SET/RESET latches.  So it is
possible to generate all logic combinations waves with the same logic
macro function.  See the example Fig. 1.

      Signal generation with programming steps = Cycle time/8

Programming is obtained with the following set and reset words:

   set word1 = 1000 0000      set word2 = 0100 0100
 reset word1 = 0010 0000    reset word2 = 0010 0001

      The system clock is composed of 4 different parts (Fig. 2):

o   External 4 phases oscillator (1 per chip)
o   Master Ring (1 per chip)
o   Pseudo Memory 2 x 8 bits (1 per signal)
o   Logical macro function (1 per signal)

4 phases oscillator - The oscillator generates the initial period
"T0" and fixes the programming step.  step = T0/4

      Master Ring - It divides the oscillator frequency and fixes the
cycle time.  Ele mentary pulses are obtained by combination of
outputs 2 by 2 (Fig. 3).

      Cycle time = T0 x 2 x Ncell      Ncell=Number of cells in the
loop.

      Pseudo Memory - It is used to store the chosen configuration at
power on.  It is a shift register of size  = (2 x nu...