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Electrical Test Structure for Accurate Measurement of Line Width Tolerance of Ultra-Narrow MOS FET Gates

IP.com Disclosure Number: IPCOM000105081D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Burghartz, JN: AUTHOR [+2]

Abstract

An electrical test structure for the measurement of the width of very narrow gate lines of MOS FETs is disclosed. The structure is configured as a 4-point resistor structure. Similar conventional test structures rely on a measurement of the resistance of the narrow gate poly line, and correlate the measured resistance with the line width. This method is limited by the typically large variation of the resistivity of the polysilicon across the wafer (or silicided polysilicon). Thus, accurate measurements of line width and tolerance are difficult if the lines are very narrow (<0.2 &mu.m). The proposed test structure is configured as an implanted resistor in bulk silicon which is bounded by a recessed oxide (ROX) and by polysilicon gate lines (Fig. 1a,b).

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Electrical Test Structure for Accurate Measurement of Line Width Tolerance of Ultra-Narrow MOS FET Gates

      An electrical test structure for the measurement of the width
of very narrow gate lines of MOS FETs is disclosed.  The structure is
configured as a 4-point resistor structure.  Similar conventional
test structures rely on a measurement of the resistance of the narrow
gate poly line, and correlate the measured resistance with the line
width.  This method is limited by the typically large variation of
the resistivity of the polysilicon across the wafer (or silicided
polysilicon).  Thus, accurate measurements of line width and
tolerance are difficult if the lines are very narrow (<0.2  &mu.m).
The proposed test structure is configured as an implanted resistor in
bulk silicon which is bounded by a recessed oxide (ROX) and by
polysilicon gate lines (Fig. 1a,b).  The resistivity of an implanted
silicon region has a much smaller tolerance across the wafer compared
to polysilicon.  The calculation of the spacing S sub x from the
electrical resistance measurements lets one determine the poly line
width L.  The accuracy of line width tolerance measurements by using
this method should be more accurate compared to the poly-line
resistance measurements.

      One difficulty with the proposed structure may result from the
fact that advanced lithography (X-ray, Phase-Shift, Eximer laser...)
provides improved line width capability but not necessarily improved
over...