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Browse Prior Art Database

On-Card Sequencer Engine for Providing Control for Self-Test Operation

IP.com Disclosure Number: IPCOM000105099D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Ratiu, IM: AUTHOR [+2]

Abstract

An On-Card Sequencer (OCS) is provided to run diagnostic routines referred to as Built In Self-Test (BIST) of the same type utilized during a manufacturing process and the ability to log out information during a machine operation failure so that the internal contents may be analyzed and duplicated to resolve a problem.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

On-Card Sequencer Engine for Providing Control for Self-Test Operation

      An On-Card Sequencer (OCS) is provided to run diagnostic
routines referred to as Built In Self-Test (BIST) of the same type
utilized during a manufacturing process and the ability to log out
information during a machine operation failure so that the internal
contents may be analyzed and duplicated to resolve a problem.

      The On-Card Sequencer resides between an External Support
Processor (ESP) and a set of chips with which it will communicate.
As illustrated in the accompanying figure, the On-Card Sequencer
communicates with a Common On-Chip Processor via a special set of
interfaces comprising a serial data line and a control line.  All
information (i.e., chip address, command and data) is passed over the
serial line.  The control line is utilized to obtain the COP's
attention, define when the end of chip addressing and command are
complete and execute operation.

      When power is first applied to the computer the power supply
provides a POWER GOOD signal to the On-Card Sequencer which in turn
provides a HARDWARE RESET signal to the Computer Electronics Complex,
some external hardware and places any chips containing a Common
On-Chip Processor (COP) into a state which permits communication with
the On-Card Sequencer.

      After the HARDWARE RESET line is triggered, the On-Card
Sequencer transmits information for running the Built In Self-Test.
This typically comprises individually addressing each chip,
transmitting test commands, transmitting required data such as self
test needs and then instructing the COP to execute the operation.
After a short period of time the On-Card Sequencer then polls all
COPs and determines from the return status if the chips have
completed the operation.  The On-Card Sequencer then requests from
each COP the "signature" of the accumulated self-test operation.  If
the acquired signature...