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Browse Prior Art Database

Logical Directory for Real Address-Based Cache

IP.com Disclosure Number: IPCOM000105111D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 6 page(s) / 280K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

Disclosed are techniques for utilizing logical directory in designing real address based processor caches. The number of line entries in the front-end logical cache directory may be smaller than that of the actual cache, so that synonym problem is alleviated or eliminated. A backend real address directory is used for resolving logical directory misses and cross-interrogates. The selection of cache congruence class is based on certain early resolution of needed real address bits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 19% of the total text.

Logical Directory for Real Address-Based Cache

      Disclosed are techniques for utilizing logical directory in
designing real address based processor caches.  The number of line
entries in the front-end logical cache directory may be smaller than
that of the actual cache, so that synonym problem is alleviated or
eliminated.  A backend real address directory is used for resolving
logical directory misses and cross-interrogates.  The selection of
cache congruence class is based on certain early resolution of needed
real address bits.

      The concern was with computer cache design in a virtual memory
system.  The address issued for cache accessing (e.g., from I/E-unit)
is called logical address, which can be either virtual or real
depending upon the particular mode of addressing.  In a more
straightforward design, the cache is addressed through real address
only.  That is, the congruence class selection is based on real
address bits, and each cache directory entry records the real address
identifier of the associated line.  Such real address based cache
design however, often causes difficulties in efficient implementation
due to the need of virtual address translation before array accessing
can be initiated.  The IBM/3090* design (which also records real
address tags at directory entries) avoids such in-line virtual
address translation by placing a newly fetched line into the
(principal) congruence class determined by the logical address that
causes the miss fetch.  Although this approach allows faster cache
array reading it has the so-called synonym problem, for which the
resolution may cause significant complexity for bigger caches.  There
have also been designs that are logical address based, in which not
only congruence class selection is based on logical address bits but
also logical address tags are recorded in directory entries.  The
advantage of logical directory is faster address matching for great
majority of cache accesses without having to obtain translation
information from TLB.  Such approach again requires the complexity
for synonym resolution (e.g., upon logical directory misses or upon
multiprocessor cross-interrogates).  Another disadvantage of
conventional logical address directory is that, in many systems
(e.g., with 64-bit virtual addressing), the amount of bits for the
directory can be costly (especially for a large cache).  Generally
speaking, a highly desirable design approach is to have a real
address based cache for which the directory lookup for processor
access is through logical address with reasonable complexity.  This
disclosure provides such an approach.

      THE INVENTION - Consider a typical real address based cache,
for which physical lines are placed by real address bits with a real
address directory DR recording real address tags for line entries.
In addition, a front-end logical directory DL is used for the lookup
of majority of cache accesses by the processor.  The figure...