Browse Prior Art Database

Gull-Wing Floating Gate EEPROM Cell With Poly Bit Lines and Word Lines

IP.com Disclosure Number: IPCOM000105117D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 98K

Publishing Venue

IBM

Related People

Acovic, A: AUTHOR [+2]

Abstract

An EEPROM cell with a gull-wing floating gate to improve coupling factor is realized by a triple poly process. The triple poly process plus an inner poly sidewall provides ultra-shallow source/drain junctions, short channel length, low bit-line resistance and two FN tunneling surfaces, which, together with high coupling factor, significant improve the EEPROM performance.

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Gull-Wing Floating Gate EEPROM Cell With Poly Bit Lines and Word Lines

      An EEPROM cell with a gull-wing floating gate to improve
coupling factor is realized by a triple poly process.  The triple
poly process plus an inner poly sidewall provides ultra-shallow
source/drain junctions, short channel length, low bit-line resistance
and two FN tunneling surfaces, which, together with high coupling
factor, significant improve the EEPROM performance.

      Performance (program/erase/read speed), cell size and operating
voltage are the key concerns in designing EEPROM cells.  Using the
Fowler-Nordheim (FN) tunneling instead of channel hot carrier
injection as programming tools can reduce the power consumption and
thus allow a large amount of cells to be programmed at the same time.
Consequently, less programming time per cell is needed while using FN
tunneling to program EEPROM cells.  However, FN tunneling occurs at
higher voltage, which requires large power supply voltage or high
coupling factor.  High coupling factor can be realized by scaling
down the thickness of the oxide between control and floating gates or
increasing the overlap area between the floating gate and field
oxide.  Unfortunately, scaling down the thickness of the oxide
between control and floating gates will degrade the retention time of
EEPROM cells and increasing overlap area between the floating gate
and field oxide will increase cell size.  Although, increasing FN
tunneling area can also improve program/erase speed but the cell size
increases as well.

      A typical method of improving the performance (read speed) and
density of stack-gate NVRAM is to scale down the cell size by going
for more aggressive design rules.  To realize a cell with Leff less
than 0.3 &mu.m usually requires costly X-ray lithography or time
consuming E-beam lithography, or sophisticated phase-shift-mask
optical lithography.  Furthermore, for a device with Leff less than
0.25 &mu.m, short channel effects will shift the threshold voltage
and increase the off current unless ultra-shallow S/D junctions are
formed.  To implant an ultra-shallow junction, a more complicated
process such as pre-amorphorization step or different implanted dose
is usually required.

      Disclosed is a EEPROM cell having a gull-wing floating gate on
the top of the active region, FN tunneling poly sidewalls (S/D
extensions) and heavily-doped poly bit lines (figure).  The poly bit
lines drive in ultra-shallow source/drain junctions and form poly
sidewalls to realize 1) short Leff with loose ground rules and 2) FN
tunneling surfaces.  The poly bit lines with isolation layers on the
top enable a g...