Browse Prior Art Database

16 MB Three Port Memory Card for Communication Controllers

IP.com Disclosure Number: IPCOM000105128D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 104K

Publishing Venue

IBM

Related People

Aznar, A: AUTHOR [+4]

Abstract

Disclosed is the concept retained to upgrade the Memory of Communication Controllers of the IBM 3745 type. Memory can be accessed simultaneously from three independent ports. One is dedicated to the processor while the two others are for DMA's (Direct Memory Access). The three ports are served together and time share the main memory. The memory bandwidth is dynamically managed by the memory controller that dispatches the avail able bandwidth to the three users up to their maximum throughput.

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16 MB Three Port Memory Card for Communication Controllers

      Disclosed is the concept retained to upgrade the Memory of
Communication Controllers of the IBM 3745 type.  Memory can be
accessed simultaneously from three independent ports.  One is
dedicated to the processor while the two others are for DMA's (Direct
Memory Access).  The three ports are served together and time share
the main memory.  The memory bandwidth is dynamically managed by the
memory controller that dispatches the avail able bandwidth to the
three users up to their maximum throughput.

      To take advantage of the page mode access of dynamic memories,
conflicting requirements have to be resolved on how long a single
user can be served while others are waiting.  Serving a single user
for a long period of time permits to better takes advantage of the
sequential page mode or static column mode addressing of modern
dynamic memories while this prevents the memory from being shared by
the other users.

      On a four byte memory interface typical peak value of data
through put that can be achieved today is bounded to 25 Mbyte/Sec if
not using the page mode at all while page mode addressing tends to a
value three time higher i.e: 75 Mbyte/sec.  This later value would be
easily sus tained by a whole static memory however 4 time less denser
and more expensive.

      Then the  challenge for the designer consists in trying to be
as close as possible to the maximum achievable value in page mode
while keeping the latency of each user to its minimum so they are
served at their maximum throughput with no or little delay, thus
implementing a multiport concept in which each user "sees" the memory
as it would be its own.

      The solution is to dynamically share the memory between the
three users.  Long accesses in page mode dedicated to a single user
are prohib ited.  A trade off is made on the length of the accesses:
they must be long enough to take advantage of the page mode
addressing and suffi ciently short to permit a fast switching between
users.

      Following, which meets the performance objective for the
machine, has been retained.  The only basic operations that are
executed by the control on the memory interface when serving DMA or
Processor requests are:

      The above combined with a 2/2/1 worst case dispatching cycle
(cor responding...