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Four Square Folded Bitline Stacked Dram Cell with Planar Access Device Using Spacer Techniques

IP.com Disclosure Number: IPCOM000105151D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 152K

Publishing Venue

IBM

Related People

Rajeevakumar, TV: AUTHOR

Abstract

Proposed here is a high density folded bitline stacked DRAM cell with planar access device and a cell area of only 4 lithographic squares. The storage capacitor is placed above the access device, and is contacted to the device using a poly strap. Two levels of wiring are used to form bitlines, and two bitline contacts are made using the area conventionally used by one contact, thereby reducing the cell area by 4 lithographic squares. In addition, the true and complement bitlines have a neutral line between them, thereby significantly reducing the line to line coupling capacitance and noise sensitivity.

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Four Square Folded Bitline Stacked Dram Cell with Planar Access Device Using Spacer Techniques

      Proposed here is a high density folded bitline stacked DRAM
cell with planar access device and  a cell area of only 4
lithographic squares.  The storage capacitor is placed above the
access device, and is contacted to the device using a poly strap.
Two levels of wiring are used to form bitlines, and two bitline
contacts are made using the area conventionally used by one contact,
thereby reducing the cell area by 4 lithographic squares.  In
addition, the true and complement bitlines have a neutral line
between them, thereby significantly reducing the line to line
coupling capacitance and noise sensitivity.

      Fig. 1 shows the schematic vertical structure of such a DRAM
cell.  Planar access devices are located on each side of the contact
isolation trench.  Each stack capacitor is placed above the access
device and is contacted to the access device using a poly spacer.
Two contacts are formed using the area used by one conventional
contact.  Both the storage capacitor contact and the bitline contact
to the access device are made using thick poly spacers placed on each
side of the gate stack.  A shallow isolation trench filled with oxide
isolates one contact from the adjacent ones.  A 'crown'-type stacked
capacitor is shown in the schematic, as an example.  However, other
types of stacked capacitor may be used in lieu of the 'crown' type.

      Fig. 2 shows the top view (layout).  The masking levels STACK
POLY1, STACK POLY2, and PLATE are used for forming the stacked
capacitor.  Three contact masking levels, CONTACT, CONTACT1, and
CONTACT2 are used.  CONTACT connects the poly landing pad to stacked
capacitor.  CONTACT1 and CONTACT2 are used for making spacer
contacts.  BITLINE1 T and BITLINE1 C are the true and complement
bitlines connected to sense amplifiers on one side of the array.
Similarly, BITLINE2 T and BITLINE 2 C are true and complement
bitlines connected to sense amplifiers on the other side of the
array.  BITLINE1 and BITLINE2 alternates within the array, thereby
reducing the line to line coupling capacitance and noise sensitivity.
CONTACT1 is used to contact BITLINE1 T and BITLINE1 C to each access
transistors.  BITLINE2 T and BITLINE2 C is contacted to each access
transistors using CONTACT2.  As may be seen from the schematic shown
in Fig.  2, the area per cell is 4 lithographic squares.  There is
LOCOS isolation directly under BITLINE2 T and BITLINE2 C. In
addition, the isolation trench between contacts also provides device
isolation.  A simple method of fabricating the cell structure shown
in Fig.  1 is outlined below.

      After the LOCOS formation, gate oxide is formed followed by
gate stack formation.  The gate stack consists of
Poly/Nitride/Poly/Nitride layers.  This is followed by oxide collar
formation followed by source/drain implantation, as sho...