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Mechanism for Reducing Cache Port Contention During Cache Miss Processing

IP.com Disclosure Number: IPCOM000105155D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Driscoll, G: AUTHOR [+4]

Abstract

Method and apparatus are set forth to reduce the time penalty for a cache miss utilizing a "putaway" buffer for storing therein a missed line. When a line is requested from the cache, and the requested line is not stored therein, the line is transferred from main memory into the "putaway" buffer following the line miss at the cache, with the line then being transferred from the buffer to the cache at the next line miss at the cache. During the time that the missed line is stored in the buffer, the I-unit and the E-unit may access the line stored in the buffer, prior to the line being transferred to the cache.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Mechanism for Reducing Cache Port Contention During Cache Miss Processing

      Method and apparatus are set forth to reduce the time penalty
for a cache miss utilizing a "putaway" buffer for storing therein a
missed line.  When a line is requested from the cache, and the
requested line is not stored therein, the line is transferred from
main memory into the "putaway" buffer following the line miss at the
cache, with the line then being transferred from the buffer to the
cache at the next line miss at the cache.  During the time that the
missed line is stored in the buffer, the I-unit and the E-unit may
access the line stored in the buffer, prior to the line being
transferred to the cache.

      In present cache organizations, a line of data is transferred
to the cache whenever a cache miss is detected.  The time required to
transfer the line can be described by the following phases.

o   Access time - The time needed to transfer the first word (target
    address of the miss from memory to the cache).  This length of
    time largely depends on the memory speed.

o   Putaway time - The time needed to store the entire line in the
    cache.  For a cache organization having an 8 byte wide port and a
    128 byte line, this period is 16 cycles.

Typically, during the initial cycles of the access period of the
cache miss, the processor (pipeline) comes to a halt as successive
elements of the machine begin to wait for the necessary data.  The
pipeline remains idle until the data that caused the miss arrives at
the cache.  Then the data is made available to the instruction
(i)-unit and the execution (E)-unit.  When the data arrives at the
cache (and at the other elements of the machine), the pipeline again
becomes active.  During this initial reactivation of the pipleine,
the I and E units are trying to access the cache.  At the same time,
the missed cache line is competing for a cache port, through which to
be stored in the cache.  Because the cache has fewer ports than there
are resources competing for a port (I-unit, E-unit, miss facility),
certain requests are rejected.  A priority scheme is used to decide
which requests are accepted.  Typically, the line putaway is given
the highest priority, then the E-unit requests and finally, the
I-unit...