Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Carry-In Selection for Three Leg Adder in a Dependent Adder Instruction Sequence

IP.com Disclosure Number: IPCOM000105166D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 8 page(s) / 207K

Publishing Venue

IBM

Related People

Ray, DS: AUTHOR [+2]

Abstract

In the Fixed Point dual execution unit processor design, the second execution unit contains a three operand adder that allows the Fixed Point chip to execute two dependent add operations in one cycle [1]. In order to perform this feat, the two carries into the second adder must be set correctly for the operation being performed. See Fig. 1 for a diagram of the adders found in the execution units.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 33% of the total text.

Carry-In Selection for Three Leg Adder in a Dependent Adder Instruction Sequence

      In the Fixed Point dual execution unit processor design, the
second execution unit contains a three operand adder that allows the
Fixed Point chip to execute two dependent add operations in one cycle
[1].  In order to perform this feat, the two carries into the second
adder must be set correctly for the operation being performed.  See
Fig. 1 for a diagram of the adders found in the execution units.

      The adder unit for the first execution unit is a 32 bit 2 input
carry lookahead adder with 1 carry-in; it produces a 32 bit sum.  The
adder receives its 2 inputs from the A0_latch and the B0_latch.  The
carry-in signal comes from a latch in the control logic.  The
Pipeline Control Unit loads the [RA] and [RB] operands into these
latches during the decode cycle of an adder operation.  If the
operation calls for subtraction (e.g.  negate, subtract, compare,
etc.) then the Pipeline Control Unit loads the Boolean inverse of
[RA] in the A0_latch.  In such cases the Execution Unit sets the
input to the carry-in latch to a 1 during the decode cycle.

      The adder unit for the second execution unit is a 32 bit 3
input carry save adder with 1 carry-in, followed by a 32 bit 2 input
lookahead adder, with 1 carry-in; it produces a 32 bit sum.  The
adder receives its 3 inputs from the A1-latch, B1_latch and U1_latch.
The two carry-in signals come from two latches in the control logic.
This combination of parts is represented in Fig. 1 as a logical 3
operand adder.  The reason for using a 3 leg adder in the second
execution unit is that it allows us to execute inherently sequential
operations, such as:

                    A R1,R2,R3
                    A R4,R1,R5
in one cycle.  Note how the result of the first instruction R1 is the
RA operand of the second instruction.  In a traditional computer
these two instructions must be executed sequentially in order to
produce the correct result.  In the Fixed Point chip the use of the
three leg adder allows us to execute these two instructions in
parallel.

      The three input adder has 2 independent carry-in signals.
Their effect on the sum is summarized below:

     CIN1 adds 1 to the sum (carry into bit 31)

     CIN2 adds 1 to the sum (carry into bit 31)

          C1IN C2IN Units added to LSB

                     0    0    0
                     0    1    1
                     1    0    1
                     1    1    2

      For Fixed Point chip there are several instruction pairs that
benefit from the 3 leg adder.  The instructions fall into groups:

1.  Add followed by Add 2.  Add followed by Subtract/Compare 3.
Subtract/Compare followed by Add 4.  Subtract/Compare followed by
Subtract

      Each of these 4 groups have...