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Browse Prior Art Database

LSI Low Power Oriented Layout Method with Net Switching Factors

IP.com Disclosure Number: IPCOM000105179D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 75K

Publishing Venue

IBM

Related People

Kudoh, M: AUTHOR [+3]

Abstract

Disclosed is the layout method to reduce power consumption for LSI chips. The basic idea is to perform placement and wiring with the switching factor constraints of each net using Logic Simulator, which leads to shorten nets with high switching factor like CLOCK nets.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

LSI Low Power Oriented Layout Method with Net Switching Factors

      Disclosed is the layout method to reduce power consumption for
LSI chips.  The basic idea is to perform placement and wiring with
the switching factor constraints of each net using Logic Simulator,
which leads to shorten nets with high switching factor like CLOCK
nets.

      LSI power consumption can be generally expressed by the
following equation;

      POWER=(1 over 2)bullet sum to N from i=1 lbrc (Ceff sub i +
Cnet sub i + sum to M from j=1 Cin sub j) bullet SWf sub i rbrc
bullet V sup 2 bullet F

   Cnet is net capacitance
   Ceff is effective capacitance, which is equivalent to power
      consumption in a basic macro itself.
   Cin is input capacitance of basic macro.
   N is the number of nets (except primary input nets).
   M is the number of sink macros connected to neti.
   F is the frequency of base clock in circuits.

     V is the voltage that the capacitance is charged
     T is the cycle time of the machine in ns

      SWF means Switching Factor of each net and is defined as the
number of times the circuit switches during 1000 machine cycles,
divided by 1000.  TRANSITIONS means the number of transitions per
1000 machine cycles;

      SWF = TRANSITIONS over 1000 (0  lt  SWF le  2.00)

      Switching factors of all nets in the total circuits are
generated by a logic simulator and a SWF file generator.  Test case
will be used as input to a logic simulator to calculate switching
factor.

      SWF is the number between 0 and 2.00.  In LSI chip, the SWF of
base clock is 2.00 because clock signals take two transitions in one
cycle.  SWF file generatio...