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GaAs Monolithic Microwave Integrated Circuit Successive Detection Logarithmic Amplifier

IP.com Disclosure Number: IPCOM000105181D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Nelly, D: AUTHOR

Abstract

Disclosed is an approach to successive detection logarithmic amplification which allows all circuit functions: amplification, detection and video summation, to be fabricated on a single GaAs die incorporating MESFETs and Schottky diodes. The technique can be applied to single or multiple stages, depending on dynamic range requirements.

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GaAs Monolithic Microwave Integrated Circuit Successive Detection Logarithmic Amplifier

      Disclosed is an approach to successive detection logarithmic
amplification which allows all circuit functions: amplification,
detection and video summation, to be fabricated on a single GaAs die
incorporating MESFETs and Schottky diodes.  The technique can     be
applied to single or multiple stages, depending on dynamic    range
requirements.

      The schematic as referred to in the figure consists of an
amplifier A1 with RF gain, G whose output is split through a
resistive power divider between a succeeding stage and a detector
circuit.  Diode, D1 is forward biased through R1 and provides the
logarithmic voltage conversion.  The detected voltage, V1 is
converted to a video current, I1, through the enhancement mode FET,
Q1 whose bias point is determined by resistors R1, R2, and R3 and
supply voltages VGG and VDD.  The current conversion is achieved with
the FET relationship:
      &Delta.Ids    =    Gm *  &Delta.Vgs    where
 &Delta.Vgs = change in detected voltage over amplifier dynamic
range,
  Gm  = FET transconductance, and
 &Delta.Ids = resultant change in drain-source current.

      For multiple stages the drains of each FET are common and act
as the video output.