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Sequencing the DWs from a Partial Write Back

IP.com Disclosure Number: IPCOM000105184D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+2]

Abstract

The sequence in which the DWs, within a cache line on which a miss has occurred, arrive at the requesting processor can have a performance impact. This is applied to the process of partial write-back from a line that is held exclusive within another processor's cache in a (WI-L1, WI-L2) memory hierarchy. The coordination of the transfer of the DWs from the two sources, partially offset in time, is by using the DW-VALID bits maintained within the cache-miss-line-buffer. This coordination provides for a reduction in line transfer time as well as benefitting from out-of-sequence arrival of the DWs that are most likely to be used first, those from the partial writeback.

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Sequencing the DWs from a Partial Write Back

      The sequence in which the DWs, within a cache line on which a
miss has occurred, arrive at the requesting processor can have a
performance impact. This is applied to the process of
partial write-back from a line that is held exclusive within
another processor's cache in
a (WI-L1, WI-L2) memory hierarchy.
The coordination of the transfer of the DWs from the two
sources, partially offset in time, is by using
the DW-VALID bits maintained within the cache-miss-line-buffer.
This coordination provides for a reduction in line transfer
time as well as benefitting from
out-of-sequence arrival of the DWs that are most likely
to be used first, those from the partial writeback.

       Following a cache miss, the initial DW requested by the
processor is returned as the first DW of the line and in some
processor
designs upstreaming of successive DWs are presented to the
requesting unit. The basic idea is that DWs within the line
might be required close-in-time to the time of return of
the DW requested. If the line being returned is placed in a
line buffer, so that access to the other DWs in the cache can be
serviced without contention for the cache bus, said line buffer
is equipped with DW-VALID bits to attest to the validity of their
contents when accessed in parallel with normal cache accesses.

       A provision for resequencing the DWs within a cache line
based on historical usage patterns within the line buffer
can utilize these DW-VALID bits and allow the processor an
earlier access to within-missed-line DWs than provided by
the default sequence of DW arrivals. The default sequence starts
with the DW accessed and then transfers upstream DWs until the
line boundary is encountered. The lower numbered DWs within the
line are then transferred.

       In a multiprocessing system which has a Write-In L1 and
a Write-In L2, (WI, WI) a provision can be made
within the processor cache to
record the DWI, Double Word Index, of the DWs within the line
that have been modified. In the case of a XI (cross-invalidate)
induced CAST-OUT, the cache which holds the line EXCLUSIVE
perform...