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Browse Prior Art Database

Data Reordering System for Error Correction Codes

IP.com Disclosure Number: IPCOM000105196D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 164K

Publishing Venue

IBM

Related People

Karp, J: AUTHOR [+2]

Abstract

A data reordering system is disclosed that reduces circuit count and improves performance for data processing machines such as tape drives that must process information recorded in two or more recording formats. Specifically, this system is used in the 3490E tape controller to allow the processing of both 3490E tape format utilizing a Reed-Solomon (RS) Error Correction Code, and the 3480 tape format utilizing the Adaptive Cross Parity (AXP) Error Correction Code.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Data Reordering System for Error Correction Codes

      A data reordering system is disclosed that reduces circuit
count and improves performance for data processing machines such as
tape drives that must process information recorded in two or more
recording formats.  Specifically, this system is used in the 3490E
tape controller to allow the processing of both 3490E tape format
utilizing a Reed-Solomon (RS) Error Correction Code, and the 3480
tape format utilizing the Adaptive Cross Parity (AXP) Error
Correction Code.

      Fig. 1A is a block diagram of the dual format read dataflow
that processes both AXP and Reed Solomon (RS) data formats.  The AXP
and RS frame formats are depicted in Figs. 1B and 1C.  To maximize
the reuse of existing circuits and microcode, the existing AXP track
frame format was maintained for the RS code.  This involved placing
the RS parity symbols at the same locations in the frame that the AXP
parity symbols occupy in AXP mode.  Additionally, the same track
processing sequence was maintained for the RS code as for the AXP
code.  While this produces a very unusual ordering of the RS code
symbols, it allows the reuse of many of the AXP processing circuits
in the RS mode, thus significantly reducing the circuit count.  For
example, the Deskew Buffer, AXP delay buffer, and CRC circuit may all
be reused in the RS mode with no changes.  If the RS symbol order had
been designed in the traditional manner, all these circuits would be
duplicated for the RS mode of operation.

      Since the 3490E machine must be capable of reading the 3480
format, the AXP decoder and all of its circuitry must reside within
the machine.  Maintaining the identical track data and parity format
and track processing order from tape (which would require complete
duplication of many AXP circuits), a small Reorder buffer is added to
reorder the data symbols for use by the RS Syndrome function as
described below.  The reordering system consists of three elements:

o   Special format design with the RS parity symbols replacing the
    AXP parity symbols as depicted in Figs. 1A and 1B.  AXP Forward
    or AXP Backward sequence while outputting data to the RS Syndrome
    Generator in the RS Encoder order.
o   A Reordering Buffer circuit which receives data in the AXP
    Forward or AXP Backward sequence while outputting data to the RS
    Syndrome Generator in the RS Encoder order.
o   A special RS ECC function which receives data symbols in the
    reordered RS Encoder sequence, but receives Pointer i...