Browse Prior Art Database

A Scheme for Detecting Violation of Private Access in a Multiprocessor System

IP.com Disclosure Number: IPCOM000105199D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Stone, JM: AUTHOR

Abstract

A processor in a multiprocessor system that has the privilege of private access to a set of shared-memory locations may gain a performance advantage by accessing those locations noncoherently. This disclosure gives a method, composed of enhancements to cache design and to an operating-system, for detecting and recovering from a violation of private access, when a processor reads or writes a shared location that is accessed privately by another processor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

A Scheme for Detecting Violation of Private Access in a Multiprocessor System

      A processor in a multiprocessor system that has the privilege
of private access to a set of shared-memory locations may gain a
performance advantage by accessing those locations noncoherently.
This disclosure gives a method, composed of enhancements to cache
design and to an operating-system, for detecting and recovering from
a violation of private access, when a processor reads or writes a
shared location that is accessed privately by another processor.

      A multiprocessor with cache memories at each processor normally
maintains coherence in the values in its caches by granting ownership
to a single writer at a time and notifying other caches when a value
is modified by a writer.  For a restricted class of applications, in
which processors access separate areas of memory, a performance
improvement can be obtained by foregoing cache coherence.  This
technique has a drawback for program development, because it will be
difficult to detect a programming error in which one processor
accesses with coherence enabled an area that is being accessed by
another processor with coherence disabled.  The cache of the
processor with coherence disabled can detect the unexpected access,
but current cache implementations have no way to communicate this to
the processor.

      Assume that the multiprocessor uses a write-invalidate protocol
and that cache coherence is enabled or disabled according to the
setting of a bit associated with each page of memory.  The operatin...